JAJSLB7A March   2021  – December 2023 TUSB216I

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Speed Boost
      2. 7.3.2 RX Sensitivity
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Speed (LS) Mode
      2. 7.4.2 Full-Speed (FS) Mode
      3. 7.4.3 High-Speed (HS) Mode
      4. 7.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 7.4.5 Shutdown Mode
      6. 7.4.6 I2C Mode
      7. 7.4.7 BC 1.2 Battery Charging Controller
    5. 7.5 TUSB216 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Requirements

MIN NOM MAX UNIT
POWER UP TIMING
TRSTN_PW Minimum width to detect a valid RSTN signal assert when the pin is actively driven low 100 µs
TSTABLE VCC must be stable before RSTN de-assertion 300 µs
TREADY Maximum time needed for the device to be ready after RSTN is de-asserted. 500 µs
TRAMP VCC ramp time 100 ms
TRAMP VCC ramp time 0.2 ms
I2C (STD)
tSUSTO Stop setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD  4     µs
tHDSTA Start hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 4     µs
tSUSTA Start setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 4.7 µs
tSUDAT Data input or False start/stop, setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 250 ns
tHDDAT Data input or False start/stop, hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 5 µs
tBUF Bus free time between START and STOP conditions 4.7 µs
tLOW Low period of the I2C clock 4.7 µs
tHIGH High period of the I2C clock 4 µs
tF Fall time of both SDA and SCL signals 300 ns
tR Rise time of both SDA and SCL signals 1000 ns
I2C (FM)
tSUSTO Stop setup time, SCL (Tr=180ns-300ns), SDA (Tf=6.5ns-106.5ns), 400 kHz FM 0.6 µs
tHDSTA Start hold time, SCL (Tr=180ns-300ns), SDA (Tf=6.5ns-106.5ns), 400 kHz FM 0.6 µs
tSUSTA Start setup time, SCL (Tr=180ns-300ns), SDA (Tf=6.5ns-106.5ns), 400 kHz FM 0.6 µs
tSUDAT Data input or False start/stop, setup time, SCL (Tr=180ns-300ns), SDA (Tf=6.5ns-106.5ns), 400 kHz FM 100 ns
tHDDAT Data input or False start/stop, hold time, SCL (Tr=180ns-300ns), SDA (Tf=6.5ns-106.5ns), 400 kHz FM 0 µs
tBUF Bus free time between START and STOP conditions 1.3 µs
tLOW Low period of the I2C clock 1.3 µs
tHIGH High period of the I2C clock 0.6 µs
tF Fall time of both SDA and SCL signals 300 ns
tR Rise time of both SDA and SCL signals 300 ns