JAJSK22 June   2021 TUSB217A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High-Speed Boost
      2. 8.3.2 RX Sensitivity
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Speed (LS) Mode
      2. 8.4.2 Full-Speed (FS) Mode
      3. 8.4.3 High-Speed (HS) Mode
      4. 8.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 8.4.5 Shutdown Mode
      6. 8.4.6 I2C Mode
      7. 8.4.7 BC 1.2 Battery Charging Controller
    5. 8.5 TUSB217A Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 9.2.2.1.1 For a Host Side Application
          2. 9.2.2.1.2 For a Device Side Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
POWER
IACTIVE_HS High Speed Active Current USB channel = HS mode. 480 Mbps traffic. VCC supply stable, with Boost = Max 22 36 mA
IIDLE_HS High Speed Idle Current USB channel = HS mode, no traffic. VCC supply stable, Boost = Max 22 36 mA
IHS_SUPSPEND High Speed Suspend Current USB channel = HS Suspend mode. VCC supply stable 0.75 1.4 mA
IFS Full-Speed Current USB channel = FS mode, 12 Mbps traffic, Vcc supply stable 0.75 1.4 mA
IDISCONN Disconnect Power Host side application. No device attachment. 0.80 1.4 mA
ISHUTDN Shutdown Power RSTN driven low, VCC supply stable 60 115 µA
CONTROL PIN LEAKAGE
ILKG_FS Pin failsafe leakage current for SDA, RSTN VCC = 0 V, pin at VIH, max 10 15 µA
ILKG_FS Pin failsafe leakage current for RX_SEN VCC = 0 V, pin at VIH, max 6 15 µA
ILKG_FS Pin failsafe leakage current for SCL VCC = 0 V, pin at VIH, max 70 nA
INPUT RSTN
VIH High level input voltage 1.5 3.6 V
VIL Low-level input voltage 0 0.5 V
IIH High level input current VIH = 3.6 V, RPU enabled ±15 µA
IIL Low level input current VIL = 0V, RPU enabled ±20 µA
INPUT DIGITAL
VIH High level input voltage (DCP/CDP) 1.5 3.6 V
VIL Low-level input voltage (DCP/CDP) 0 0.5 V
IIL Low level input current VIL = 0V ±20 µA
IIH High level input current VIH = 3.6 V ±15 µA
INPUT RX_SEN (3-level input, for mid level leave pin floating)
VIH(Max) Maximum High level input voltage 

 		 VCC = 2.3V to 6.5V  5.0 V
VIH(Min) Minimum High level input voltage


 		 VCC > 4.5V 3.3 V
VCC = 2.3V to 4.5V (% of VCC) 75 %
VIL Low level input voltage


 		 VCC > 4.5V 0.75 V
VCC = 2.3V to 4.5V (% of VCC) 15 %
INPUT BOOST
RBOOST_LVL0 External pulldown resistor for BOOST Level 0 160 Ω
RBOOST_LVL1 External pulldown resistor for BOOST Level 1 1.5 1.8 2 kΩ
RBOOST_LVL2 External pulldown resistor for BOOST Level 2 3.4 3.6 3.96 kΩ
RBOOST_LVL3 External pulldown resistor  for BOOST Level 3 to remove upper limit for resistor value, can be left open 7.5 kΩ
OUTPUTS CD, ENA_HS
VOH High level output voltage for CD and ENA_HS IO = –50 µA, VCC >= 3.0V 2.5 V
VOH High level output voltage  for CD IO = –25 µA, VCC = 2.3V 1.7 V
VOH High level output voltage  for ENA_HS IO = –25 µA, VCC = 2.3V 1.8 V
VOL Low level output voltage  for CD and ENA_HS IO = 50 µA 0.3 V
I2C
CI2C_BUS I2C Bus Capacitance 4 150 pF
IOL I2C open drain output current VOL = 0.4V 1.5 mA
VIL 2.3V<= VCC<= 4.3V, VI2C_BUS = 1.8V +/-10% RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS 25 %
VIL VI2C_BUS = 3.3V +/-10% RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS 25 %
VIH 2.3V<= VCC<= 4.3V, VI2C_BUS = 1.8V +/-10% RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS 80 %
VIH VI2C_BUS = 3.3V +/-10% RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS 75 %
RPull-up VI2C_BUS = 1.8V +/-10% 1.6 2 2.5 kΩ
RPull-up VI2C_BUS = 3.3V +/-10% 2.8 4.7 7 kΩ
SCL Frequency 100 kHz
DxP, DxM
CIO_DXX Capacitance to GND Measured with VNA at 240 MHz, VCC supply stable, Redriver off 2.5 pF
(1) All typical values are at VCC = 5 V, and TA = 25°C.