SNLS757 Data sheet

SNLS757 June 2024 TUSB2E221

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メカニカル・データ（パッケージ｜ピン）

YCG|25
- MXBG410

サーマルパッド・メカニカル・データ

発注情報

snls757_oa

10.1 TUSB2E221 Registers

Table 10-1 lists the memory-mapped registers for the TUSB2E221 registers. All register offset addresses not listed in Table 10-1 should be considered as reserved locations and the register contents should not be modified.

Table 10-1 TUSB2E221 Registers

Offset	Acronym	Register Name	Section
0h	GPIO0_CONFIG	RAP Register for Port 0 (30h)	Go
10h	LOPWR_N_UART_P0		Go
20h	CONFIG_PORT0	RAP Register for Port 0 (10h)	Go
30h	U_TX_ADJUST_PORT0	RAP Register for Port 0 (0h), Default through OTP	Go
31h	U_HS_TX_PRE_EMPHASIS_P0	RAP Register for Port 0 (1h), Default through OTP	Go
32h	U_RX_ADJUST_PORT0	RAP Register for Port 0 (2h), Default through OTP	Go
33h	U_DISCONNECT_SQUELCH_PORT0	RAP Register for Port 0 (3h), Default through OTP	Go
37h	E_HS_TX_PRE_EMPHASIS_P0	RAP Register for Port 0 (7h), Default through OTP	Go
38h	E_TX_ADJUST_PORT0	RAP Register for Port 0 (8h), Default through OTP	Go
39h	E_RX_ADJUST_PORT0	RAP Register for Port 0 (9h), Default through OTP	Go
40h	GPIO1_CONFIG	RAP Register for Port 1 (30h)	Go
50h	LOPWR_N_UART_P1		Go
60h	CONFIG_PORT1	RAP Register for Port 1 (10h)	Go
70h	U_TX_ADJUST_PORT1	RAP Register for Port 1 (0h), Default through OTP	Go
71h	U_HS_TX_PRE_EMPHASIS_P1	RAP Register for Port 1 (1h), Default through OTP	Go
72h	U_RX_ADJUST_PORT1	RAP Register for Port 1 (2h), Default through OTP	Go
73h	U_DISCONNECT_SQUELCH_PORT1	RAP Register for Port 1 (3h), Default through OTP	Go
77h	E_HS_TX_PRE_EMPHASIS_P1	RAP Register for Port 1 (7h), Default through OTP	Go
78h	E_TX_ADJUST_PORT1	RAP Register for Port 1 (8h), Default through OTP	Go
79h	E_RX_ADJUST_PORT1	RAP Register for Port 1 (9h), Default through OTP	Go
A3h	INT_STATUS_1		Go
A4h	INT_STATUS_2		Go
B0h	REV_ID		Go
B2h	GLOBAL_CONFIG		Go
B3h	INT_ENABLE_1		Go
B4h	INT_ENABLE_2		Go

Complex bit access types are encoded to fit into small table cells. Table 10-2 shows the codes that are used for access types in this section.

Table 10-2 TUSB2E221 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
WtoPH	W toPH	Write Pulse high
Reset or Default Value
-n		Value after reset or the default value

10.1.1 GPIO0_CONFIG Register (Offset = 0h) [Reset = 00h]

GPIO0_CONFIG is shown in Table 10-3.

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Table 10-3 GPIO0_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO0_OD_PP	R/W	0h	GPIO0 Output Type 0h = Open drain output 1h = Push pull output
6	GPIO0_IN_TRIGGER_TYPE	R/W	0h	GPIO0 Input Trigger Type for Interrupt 0h = Edge trigger input 1h = Level trigger input (INT output will reflect the input level state)
5	GPIO0_DIRECTION	R/W	0h	GPIO0 Direction 0h = Input 1h = Output
4	GPIO0_INPUT_STATUS	RH	0h	Logical Value of GPIO0 pin input (0=Low, 1=High) 0h = Input is low 1h = Input is high
3-0	GPIO0_OUTPUT_SELECT	R/W	0h	GPIO0 Output Selection 0h = Remote Wakeup - host repeater is receiving remote wake but has not seen start of resume 1h = USB disconnect - host repeater is actively forwarding LS/FS disconnect. 2h = USB_HS_Unsquelched - host repeater in L0 seeing USB HS or in reset seeing Chirp 3h = PVTB - HOST repeater is actively transmitting ESE1 due to HS disconnect. 4h = DEFAULT - waiting to be configured host/peripheral 5h = HOST - in host repeater mode 6h = PERIPHERAL - in peripheral repeater mode 7h = CONNECTED - repeater is connected, connection seen acknowledged by start of reset 8h = RESET - reset in progress, reset is detected is high, L0 is low 9h = L0 - fully configured and repeating data, keep-alive and reset/disconnect Ah = L1 -device has received CM.FS/CM.L1,has stopped repeating and is waiting for wake/resume Bh = L2 - device has received CM.L2, has stopped repeating and is waiting for wake/resume. Ch = GPIO0_HS_TEST - in host repeater in L0 mode, received CM.TEST Dh = HIGH_OUTPUT - output is forced static high Eh = LOW_OUTPUT - output is forced static low Fh = OVP - over voltage (DP/DN voltage > VOVP_TH) detected on the USB DP/DN

10.1.2 LOPWR_N_UART_P0 Register (Offset = 10h) [Reset = 50h]

LOPWR_N_UART_P0 is shown in Table 10-4.

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Table 10-4 LOPWR_N_UART_P0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7	RESERVED	R	0h		Reserved
6	HOST_FRAME_LP_EN_P0	RH/W	1h	Y	Host repeater frame-based Low Power enable Default through OTP 0h = Not Enabled 1h = Enabled
5	DEVICE_FRAME_LP_EN_P0	RH/W	0h	Y	Peripheral repeater frame-based Low Power enable Default through OTP 0h = Not Enabled 1h = Enabled
4	IDLE_LP_EN_P0	RH/W	1h	Y	enable response-based Low Power mode Default through OTP 0h = Not Enabled 1h = Enabled
3	UART_GPI_POLARITY_P0	RH/W	0h	Y	Select polarity of pin to enable UART mode Default through OTP 0h = GPIO0 pin enables UART mode when 1 1h = GPIO0 pin enables UART mode when 0
2	UART_DP_PU_EN_P0	RH/W	0h	Y	Select whether DP pullup is enabled during UART mode Default through OTP 0h = disable DP pullup during UART mode 1h = enable DP pullup during UART mode
1	UART_en_by_reg_not_pin_P0	RH/W	0h	Y	Select whether UART mode is enabled by register or by GPIO0 pin Default through OTP 0h = select UART_mode_en_P0 register to enable UART mode 1h = select GPIO0 pin to enable UART mode
0	UART_mode_en_P0	RH/W	0h	Y	If GPIO0 is not selected to enable UART mode, this register will enable it. Default through OTP 0h = disable UART mode between eUSB2 and USB 2.0 pins 1h = enable UART mode between eUSB2 and USB 2.0 pins

10.1.3 CONFIG_PORT0 Register (Offset = 20h) [Reset = 00h]

CONFIG_PORT0 is shown in Table 10-5.

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Table 10-5 CONFIG_PORT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h	Reserved
6-5	RESERVED	R	0h	Reserved
4-3	HOST_DEVICE_P0	RH	0h	Port0 is configured as a Host repeater or a Device repeater 0h = Not configured 1h = Host repeater 2h = Device repeater 3h = Reserved
2-1	RESERVED	R	0h	Reserved
0	CDP_2_STATUS_P0	RH	0h	Primary detection detected on port0 if CDP_2_EN_P0=1 0h = CDP primary detection detected 1h = CDP primary detection not detected

10.1.4 U_TX_ADJUST_PORT0 Register (Offset = 30h) [Reset = 77h]

U_TX_ADJUST_PORT0 is shown in Table 10-6.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-6 U_TX_ADJUST_PORT0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-6	U_HS_TERM_P0	RH/W	1h	Y	Z_HSTERM adjustment USB HS Termination Adjustment (-5% to 10% in 5% steps) Default through OTP 0h = 42.75 Ω (typical) 1h = 45 Ω (typical) (hw default) 2h = 47.25 Ω (typical) 3h = 49.5 Ω (typical)
5-4	U_HS_TX_SLEW_RATE_P0	RH/W	3h	Y	T_HSR adjustment USB HS TX Slew Rate (350ps - 575ps) Default through OTP 0h = 350ps (typical) 1h = 425ps (typical) 2h = 500ps (typical) 3h = 575ps (typical) (hw default)
3-0	U_HS_TX_AMPLITUDE_P0	RH/W	7h	Y	V_EHSOD adjustment USB HS TX Amplitude, measured p-p USB 2.0 spec nominal will be 800mV (-7.5% to 30% in 2.5% steps) Default through OTP This setting has no effect on amplitude during chirp J (VCHIRPJ) or chirp K (VCHIRPK) 0h = 800mV - 7.5% , 740mV (typical) 1h = 800mV - 5.0% , 760mV (typical) 2h = 800mV - 2.5% , 780mV (typical) 3h = 800mV (USB 2.0 spec nominal) , 800mV (typical) (hw default) 4h = 800mV + 2.5% , 820mV (typical) 5h = 800mV + 5.0% , 840mV (typical) 6h = 800mV + 7.5% , 860mV (typical) 7h = 800mV + 10% , 880mV (typical) 8h = 800mV + 12.5% , 900mV (typical) 9h = 800mV + 15% , 920mV (typical) Ah = 800mV + 17.5% , 940mV (typical) Bh = 800mV + 20% , 960mV (typical) Ch = 800mV + 22.5% , 980mV (typical) Dh = 800mV + 25% , 1000mV (typical) Eh = 800mV + 27.5% , 1020mV (typical) Fh = 800mV + 30% , 1040mV (typical)

10.1.5 U_HS_TX_PRE_EMPHASIS_P0 Register (Offset = 31h) [Reset = 39h]

U_HS_TX_PRE_EMPHASIS_P0 is shown in Table 10-7.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-7 U_HS_TX_PRE_EMPHASIS_P0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7	RESERVED	RH/W	0h		Reserved
6	CDP_1_EN_P0	RH/W	0h	Y	Enables CDP using method 1 on port0 Default through OTP 0h = CDP using method 1 not enabled (hw default) 1h = CDP using method 1 enabled
5-4	U_HS_TX_PE_WIDTH_P0	RH/W	3h	Y	U2_{_TXPE_UI} Adjustment USB HS TX Pre-emphasis Width Default through OTP 0h = 0.35 UI (typical) 1h = 0.45 UI (typical) 2h = 0.55 UI (typical) 3h = 0.65 UI (typical) (hw default)
3	U_HS_TX_PE_ENABLE_P0	RH/W	1h	Y	USB HS TX Pre-emphasis Enable Default through OTP PE is disabled during chirp J (VCHIRPJ) or chirp K (VCHIRPK) 0h = Disabled (hw default) 1h = Enabled
2-0	U_HS_TX_PRE_EMPHASIS_P0	RH/W	1h	Y	U2_{_TXPE} Adjustment USB HS TX Pre-emphasis (0.5dB-4.0dB) Default through OTP PE is disabled during chirp J (VCHIRPJ) or chirp K (VCHIRPK) 0h = 0.5dB (typical) (hw default) 1h = 0.9dB (typical) 2h = 1.2dB (typical) 3h = 1.7dB (typical) 4h = 2.1dB (typical) 5h = 2.5dB (typical) 6h = 3.2dB (typical) 7h = 4.0dB (typical)

10.1.6 U_RX_ADJUST_PORT0 Register (Offset = 32h) [Reset = D2h]

U_RX_ADJUST_PORT0 is shown in Table 10-8.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-8 U_RX_ADJUST_PORT0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-6	i2c_ds_config	RH/W	3h	Y	I2C open drain output drive strength selection This is intended to be set through I2C. (It can be set through RAP only if repeater 0 is enabled) Default through OTP 0h = ~1mA (typical) 1h = ~2mA (typical) 2h = ~4mA (typical) 3h = ~8mA (typical) (hw default)
5-4	RESERVED	RH/W	1h		Reserved
3	RESERVED	RH/W	0h		Reserved
2-0	U_EQ_P0	RH/W	2h	Y	EQ_{_UHS} Adjustment USB RX Equalizer Control (0-3.35dB) Default through OTP 0h = 0.06dB (typical) (hw default) 1h = 0.58dB (typical) 2h = 1.09dB (typical) 3h = 1.56dB (typical) 4h = 2.26dB (typical) 5h = 2.67dB (typical) 6h = 3.03dB (typical) 7h = 3.35dB (typical)

10.1.7 U_DISCONNECT_SQUELCH_PORT0 Register (Offset = 33h) [Reset = 74h]

U_DISCONNECT_SQUELCH_PORT0 is shown in Table 10-9.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-9 U_DISCONNECT_SQUELCH_PORT0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-4	U_DISCONNECT_THRESHOLD_P0	RH/W	7h	Y	V_HSDSC Adjustment USB Minimum HS HOST Disconnect Threshold (0% to +57% in ~3.7% steps) Default through OTP 0h = 525mV (minimum), 0% (hw default) 1h = 545mV (minimum), +4% 2h = 565mV (minimum), +8% 3h = 585mV (minimum), +11% 4h = 605mV (minimum), +15% 5h = 625mV (minimum), +19% 6h = 645mV (minimum), +23% 7h = 665mV (minimum), +27% 8h = 685mV (minimum), +31% 9h = 705mV (minimum), +34% Ah = 725mV (minimum), +38% Bh = 745mV (minimum), +42% Ch = 765mV (minimum), +46% Dh = 785mV (minimum), +50% Eh = 805mV (minimum), +53% Fh = 825mV (minimum), +57%
3	RESERVED	RH/W	0h		Reserved
2-0	U_SQUELCH_THRESHOLD_P0	RH/W	4h	Y	V_HSSQ Adjustment USB Squelch Detection Min Threshold (+30% to -15% in ~6.5% steps) Default through OTP 0h = 130mV (minimum), +30% 1h = 124mV (minimum), +24% 2h = 117mV (minimum), +17% 3h = 111mV (minimum), +11% 4h = 104mV (minimum), +4% (hw default) 5h = 98mV (minimum), -2% 6h = 91mV (minimum), -9% 7h = 85mV (minimum), -15%

10.1.8 E_HS_TX_PRE_EMPHASIS_P0 Register (Offset = 37h) [Reset = 40h]

E_HS_TX_PRE_EMPHASIS_P0 is shown in Table 10-10.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-10 E_HS_TX_PRE_EMPHASIS_P0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-5	E_HS_TX_PRE_EMPHASIS_P0	RH/W	2h	Y	E_{_TXPE} adjustment eUSB2 HS TX Pre-emphasis 0dB-3.86dB Default through OTP 0h = 0dB (typical) (hw default) 1h = 0.67dB (typical) 2h = 1.29dB (typical) 3h = 1.87dB (typical) 4h = 2.41dB (typical) 5h = 2.92dB (typical) 6h = 3.41dB (typical) 7h = 3.86dB (typical)
4-3	E_HS_TX_PE_WIDTH_P0	RH/W	0h	Y	E_{_TXPE_UI} adjustment eUSB2 HS TX Pre-emphasis Width Default through OTP 0h = 0.35 UI (typical) (hw default) 1h = 0.45 UI (typical) 2h = 0.55 UI (typical) 3h = 0.65 UI (typical)
2	RESERVED	RH/W	0h		Reserved
1	RESERVED	RH/W	0h		Reserved
0	RESERVED	R	0h

10.1.9 E_TX_ADJUST_PORT0 Register (Offset = 38h) [Reset = 0Ch]

E_TX_ADJUST_PORT0 is shown in Table 10-11.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-11 E_TX_ADJUST_PORT0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-6	RESERVED	RH/W	0h		Reserved
5	RESERVED	RH/W	0h		Reserved
4-3	E_HS_TX_SLEW_RATE_P0	RH/W	1h	Y	T_EHSRF Adjustment eUSB2 HS TX Slew Rate 390ps - 540ps Default through OTP 0h = 390ps (typical) 1h = 440ps (typical) (hw default) 2h = 490ps (typical) 3h = 540ps (typical)
2-0	E_HS_TX_AMPLITUDE_P0	RH/W	4h	Y	V_EHSOD Adjustment eUSB2 HS TX Amplitude 360mV to 500mV (p-2-p) Default through OTP 0h = 360mV (typical) 1h = 380mV (typical) 2h = 400mV (typical) 3h = 420mV (typical) (hw default) 4h = 440mV (typical) 5h = 460mV (typical) 6h = 480mV (typical) 7h = 500mV (typical)

10.1.10 E_RX_ADJUST_PORT0 Register (Offset = 39h) [Reset = 62h]

E_RX_ADJUST_PORT0 is shown in Table 10-12.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-12 E_RX_ADJUST_PORT0 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7	RESERVED	RH/W	0h		Reserved
6-4	E_SQUELCH_THRESHOLD_P0	RH/W	6h	Y	V_EHSSQ Adjustment eUSB2 HS Squelch Detection Threshold Default through OTP 0h = 104mV (typical) 1h = 101mV (typical) 2h = 98mV (typical) 3h = 90mV (typical) 4h = 81mV (typical) 5h = 73mV (typical) 6h = 67mV (typical) (hw default) 7h = 60mV (typical)
3-0	E_EQ_P0	RH/W	2h	Y	EQ_{_EHS} Adjustment eUSB2 RX Equalizer Control Default through OTP 0h = 0.34dB (typical) (hw default) 1h = 0.71dB (typical) 2h = 1.02dB (typical) 3h = 1.36dB (typical) 4h = 1.64dB (typical) 5h = 1.94dB (typical) 6h = 2.19dB (typical) 7h = 2.45dB (typical) 8h = 2.69dB (typical) 9h = 2.93dB (typical) Ah = 3.13dB (typical) Bh = 3.35dB (typical) Ch = 3.53dB (typical) Dh = 3.72dB (typical) Eh = 3.89dB (typical) Fh = 4.07dB (typical)

10.1.11 GPIO1_CONFIG Register (Offset = 40h) [Reset = 00h]

GPIO1_CONFIG is shown in Table 10-13.

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Table 10-13 GPIO1_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO1_OD_PP	R/W	0h	GPIO1 Output Type selection 0h = Open drain output 1h = Push pull output
6	GPIO1_IN_TRIGGER_TYPE	R/W	0h	GPIO1 Input Trigger Type selection for Interrupt 0h = Edge trigger input 1h = Level trigger input (INT output will reflect the input level state)
5	GPIO1_DIRECTION	R/W	0h	GPIO1 Direction selection 0h = Input 1h = Output
4	GPIO1_INPUT_STATUS	RH	0h	Logical Value of GPIO1 pin input status (0=Low, 1=High) 0h = Input is low 1h = Input is high
3-0	GPIO1_OUTPUT_SELECT	R/W	0h	GPIO1 Output Selection 0h = Remote Wakeup - host repeater is receiving remote wake but has not seen start of resume 1h = USB disconnect - host repeater is actively forwarding LS/FS disconnect. 2h = USB_HS_Unsquelched - host repeater in L0 seeing USB HS or in reset seeing Chirp 3h = PVTB - HOST repeater is actively transmitting ESE1 due to HS disconnect. 4h = DEFAULT - waiting to be configured host/peripheral 5h = HOST - in host repeater mode 6h = PERIPHERAL - in peripheral repeater mode 7h = CONNECTED - repeater is connected, connection seen acknowledged by start of reset 8h = RESET - reset in progress, reset is detected is high, L0 is low 9h = L0 - fully configured and repeating data, keep-alive and reset/disconnect Ah = L1 -device has received CM.FS/CM.L1,has stopped repeating and is waiting for wake/resume Bh = L2 - device has received CM.L2, has stopped repeating and is waiting for wake/resume. Ch = GPIO1_HS_TEST - in host repeater in L0 mode, received CM.TEST Dh = HIGH_OUTPUT - output is forced static high Eh = LOW_OUTPUT - output is forced static low Fh = OVP - over voltage (DP/DN voltage > VOVP_TH) detected on the USB DP/DN

10.1.12 LOPWR_N_UART_P1 Register (Offset = 50h) [Reset = 50h]

LOPWR_N_UART_P1 is shown in Table 10-14.

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Table 10-14 LOPWR_N_UART_P1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7	RESERVED	R	0h
6	HOST_FRAME_LP_EN_P1	RH/W	1h	Y	Host repeater frame-based Low Power enable Default through OTP 0h = Not Enabled 1h = Enabled
5	DEVICE_FRAME_LP_EN_P1	RH/W	0h	Y	Peripheral repeater frame-based Low Power enable Default through OTP 0h = Not Enabled 1h = Enabled
4	IDLE_LP_EN_P1	RH/W	1h	Y	enable response-based Low Power mode Default through OTP 0h = Not Enabled 1h = Enabled
3	UART_GPI_POLARITY_P1	RH/W	0h	Y	Select polarity of pin to enable UART mode Default through OTP 0h = GPIO1 pin enables UART mode when 1 1h = GPIO1 pin enables UART mode when 0
2	UART_DP_PU_EN_P1	RH/W	0h	Y	Select whether DP pullup is enabled during UART mode Default through OTP 0h = disable DP pullup during UART mode 1h = enable DP pullup during UART mode
1	UART_en_by_reg_not_pin_P1	RH/W	0h	Y	Select whether UART mode is enabled by register or by GPIO1 pin Default through OTP 0h = select UART_mode_en_P1 register to enable UART mode 1h = select GPIO1 pin to enable UART mode
0	UART_mode_en_P1	RH/W	0h	Y	If GPIO1 is not selected to enable UART mode, this register will enable it. Default through OTP 0h = disable UART mode between eUSB2 and USB 2.0 pins 1h = enable UART mode between eUSB2 and USB 2.0 pins

10.1.13 CONFIG_PORT1 Register (Offset = 60h) [Reset = 00h]

CONFIG_PORT1 is shown in Table 10-15.

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Table 10-15 CONFIG_PORT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h	Reserved
6-5	RESERVED	R	0h	Reserved
4-3	HOST_DEVICE_P1	RH	0h	Port1 is configured as a Host repeater or a Device repeater 0h = Not configured 1h = Host repeater 2h = Device repeater 3h = Reserved
2-1	RESERVED	R	0h	Reserved
0	CDP_2_STATUS_P1	RH	0h	Primary detection detected on port1 if CDP_2_EN_P1=1 0h = CDP primary detection detected 1h = CDP primary detection not detected

10.1.14 U_TX_ADJUST_PORT1 Register (Offset = 70h) [Reset = 77h]

U_TX_ADJUST_PORT1 is shown in Table 10-16.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-16 U_TX_ADJUST_PORT1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-6	U_HS_TERM_P1	RH/W	1h	Y	Z_HSTERM adjustment USB HS Termination Adjustment (-5% to 10% in 5% steps) Default through OTP 0h = 42.75 Ω (typical) 1h = 45 Ω (typical) (hw default) 2h = 47.25 Ω (typical) 3h = 49.5 Ω (typical)
5-4	U_HS_TX_SLEW_RATE_P1	RH/W	3h	Y	T_HSR adjustment USB HS TX Slew Rate (350ps - 575ps) Default through OTP 0h = 350ps (typical) 1h = 425ps (typical) 2h = 500ps (typical) 3h = 575ps (typical) (hw default)
3-0	U_HS_TX_AMPLITUDE_P1	RH/W	7h	Y	V_EHSOD adjustment USB HS TX Amplitude, measured p-p USB 2.0 spec nominal will be 800mV (-7.5% to 30% in 2.5% steps) Default through OTP This setting has no effect on amplitude during chirp J (VCHIRPJ) or chirp K (VCHIRPK) 0h = 800mV - 7.5% , 740mV (typical) 1h = 800mV - 5.0% , 760mV (typical) 2h = 800mV - 2.5% , 780mV (typical) 3h = 800mV (USB 2.0 spec nominal) , 800mV (typical) (hw default) 4h = 800mV + 2.5% , 820mV (typical) 5h = 800mV + 5.0% , 840mV (typical) 6h = 800mV + 7.5% , 860mV (typical) 7h = 800mV + 10% , 880mV (typical) 8h = 800mV + 12.5% , 900mV (typical) 9h = 800mV + 15% , 920mV (typical) Ah = 800mV + 17.5% , 940mV (typical) Bh = 800mV + 20% , 960mV (typical) Ch = 800mV + 22.5% , 980mV (typical) Dh = 800mV + 25% , 1000mV (typical) Eh = 800mV + 27.5% , 1020mV (typical) Fh = 800mV + 30% , 1040mV (typical)

10.1.15 U_HS_TX_PRE_EMPHASIS_P1 Register (Offset = 71h) [Reset = 39h]

U_HS_TX_PRE_EMPHASIS_P1 is shown in Table 10-17.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-17 U_HS_TX_PRE_EMPHASIS_P1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7	RESERVED	RH/W	0h		Reserved
6	CDP_1_EN_P1	RH/W	0h	Y	Enables CDP using method 1 on port1 Default through OTP 0h = CDP using method 1 not enabled (hw default) 1h = CDP using method 1 enabled
5-4	U_HS_TX_PE_WIDTH_P1	RH/W	3h	Y	U2_{_TXPE_UI} USB HS TX Pre-emphasis Width Default through OTP 0h = 0.35 UI (typical) 1h = 0.45 UI (typical) 2h = 0.55 UI (typical) 3h = 0.65 UI (typical) (hw default)
3	U_HS_TX_PE_ENABLE_P1	RH/W	1h	Y	USB HS TX Pre-emphasis Enable Default through OTP PE is disabled during chirp J (VCHIRPJ) or chirp K (VCHIRPK) 0h = Disabled (hw default) 1h = Enabled
2-0	U_HS_TX_PRE_EMPHASIS_P1	RH/W	1h	Y	U2_{_TXPE} USB HS TX Pre-emphasis (0.5dB-4.0dB) Default through OTP PE is disabled during chirp J (VCHIRPJ) or chirp K (VCHIRPK) 0h = 0.5dB (typical) (hw default) 1h = 0.9dB (typical) 2h = 1.2dB (typical) 3h = 1.7dB (typical) 4h = 2.1dB (typical) 5h = 2.5dB (typical) 6h = 3.2dB (typical) 7h = 4.0dB (typical)

10.1.16 U_RX_ADJUST_PORT1 Register (Offset = 72h) [Reset = 92h]

U_RX_ADJUST_PORT1 is shown in Table 10-18.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-18 U_RX_ADJUST_PORT1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-6	gpio_ds_config	RH/W	2h	Y	GPIOx and INT open drain output drive strength selection This is intended to be set through I2C. (It can be set through RAP only if repeater 1 is enabled) Default through OTP 0h = ~1mA (typical) 1h = ~2mA (typical) 2h = ~4mA (typical) (hw default) 3h = ~8mA (typical)
5-4	RESERVED	RH/W	1h		Reserved
3	RESERVED	RH/W	0h		Reserved
2-0	U_EQ_P1	RH/W	2h	Y	EQ_{_UHS} Adjustment USB RX Equalizer Control (0-3.35dB) Default through OTP 0h = 0.06dB (typical) (hw default) 1h = 0.58dB (typical) 2h = 1.09dB (typical) 3h = 1.56dB (typical) 4h = 2.26dB (typical) 5h = 2.67dB (typical) 6h = 3.03dB (typical) 7h = 3.35dB (typical)

10.1.17 U_DISCONNECT_SQUELCH_PORT1 Register (Offset = 73h) [Reset = 74h]

U_DISCONNECT_SQUELCH_PORT1 is shown in Table 10-19.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-19 U_DISCONNECT_SQUELCH_PORT1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-4	U_DISCONNECT_THRESHOLD_P1	RH/W	7h	Y	V_HSDSC adjustment USB Minimum HS HOST Disconnect Threshold (0% to +57% in ~3.7% steps) Default through OTP 0h = 525mV (minimum), 0% (hw default) 1h = 545mV (minimum), +4% 2h = 565mV (minimum), +8% 3h = 585mV (minimum), +11% 4h = 605mV (minimum), +15% 5h = 625mV (minimum), +19% 6h = 645mV (minimum), +23% 7h = 665mV (minimum), +27% 8h = 685mV (minimum), +31% 9h = 705mV (minimum), +34% Ah = 725mV (minimum), +38% Bh = 745mV (minimum), +42% Ch = 765mV (minimum), +46% Dh = 785mV (minimum), +50% Eh = 805mV (minimum), +53% Fh = 825mV (minimum), +57%
3	RESERVED	RH/W	0h		Reserved
2-0	U_SQUELCH_THRESHOLD_P1	RH/W	4h	Y	V_HSSQ Adjustment USB Squelch Detection Min Threshold (+30% to -15% in ~6.5% steps) Default through OTP 0h = 130mV (minimum), +30% 1h = 124mV (minimum), +24% 2h = 117mV (minimum), +17% 3h = 111mV (minimum), +11% 4h = 104mV (minimum), +4% (hw default) 5h = 98mV (minimum), -2% 6h = 91mV (minimum), -9% 7h = 85mV (minimum), -15%

10.1.18 E_HS_TX_PRE_EMPHASIS_P1 Register (Offset = 77h) [Reset = 40h]

E_HS_TX_PRE_EMPHASIS_P1 is shown in Table 10-20.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-20 E_HS_TX_PRE_EMPHASIS_P1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-5	E_HS_TX_PRE_EMPHASIS_P1	RH/W	2h	Y	E_{_TXPE} adjustment eUSB2 HS TX Pre-emphasis 0dB-3.86dB Default through OTP 0h = 0dB (typical) (hw default) 1h = 0.67dB (typical) 2h = 1.29dB (typical) 3h = 1.87dB (typical) 4h = 2.41dB (typical) 5h = 2.92dB (typical) 6h = 3.41dB (typical) 7h = 3.86dB (typical)
4-3	E_HS_TX_PE_WIDTH_P1	RH/W	0h	Y	E_{_TXPE_UI} adjustment eUSB2 HS TX Pre-emphasis Width Default through OTP 0h = 0.35 UI (typical) (hw default) 1h = 0.45 UI (typical) 2h = 0.55 UI (typical) 3h = 0.65 UI (typical)
2	RESERVED	RH/W	0h		Reserved
1	RESERVED	RH/W	0h		Reserved
0	RESERVED	RH/W	0h		Reserved
0	RESERVED	RH/W	0h		Reserved

10.1.19 E_TX_ADJUST_PORT1 Register (Offset = 78h) [Reset = 0Ch]

E_TX_ADJUST_PORT1 is shown in Table 10-21.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-21 E_TX_ADJUST_PORT1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7-6	RESERVED	RH/W	0h		Reserved
5	RESERVED	RH/W	0h		Reserved
4-3	E_HS_TX_SLEW_RATE_P1	RH/W	1h	Y	T_EHSRF Adjustment eUSB2 HS TX Slew Rate 390ps - 540ps Default through OTP 0h = 390ps (typical) 1h = 440ps (typical) (hw default) 2h = 490ps (typical) 3h = 540ps (typical)
2-0	E_HS_TX_AMPLITUDE_P1	RH/W	4h	Y	V_EHSOD Adjustment eUSB2 HS TX Amplitude 360mV to 500mV (p-2-p) Default through OTP 0h = 360mV (typical) 1h = 380mV (typical) 2h = 400mV (typical) 3h = 420mV (typical) (hw default) 4h = 440mV (typical) 5h = 460mV (typical) 6h = 480mV (typical) 7h = 500mV (typical)

10.1.20 E_RX_ADJUST_PORT1 Register (Offset = 79h) [Reset = 62h]

E_RX_ADJUST_PORT1 is shown in Table 10-22.

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Hardware default value can be overridden through factory programmable OTP for this register.

Table 10-22 E_RX_ADJUST_PORT1 Register Field Descriptions

Bit	Field	Type	Reset	Default from OTP (Y/N)	Description
7	RESERVED	RH/W	0h		Reserved
6-4	E_SQUELCH_THRESHOLD_P1	RH/W	6h	Y	V_EHSSQ Adjustment eUSB2 HS Squelch Detection Threshold Default through OTP 0h = 104mV (typical) 1h = 101mV (typical) 2h = 98mV (typical) 3h = 90mV (typical) 4h = 81mV (typical) 5h = 73mV (typical) 6h = 67mV (typical) (hw default) 7h = 60mV (typical)
3-0	E_EQ_P1	RH/W	2h	Y	EQ_{_EHS} Adjustment eUSB2 RX Equalizer Control Default through OTP 0h = 0.34dB (typical) (hw default) 1h = 0.71dB (typical) 2h = 1.02dB (typical) 3h = 1.36dB (typical) 4h = 1.64dB (typical) 5h = 1.94dB (typical) 6h = 2.19dB (typical) 7h = 2.45dB (typical) 8h = 2.69dB (typical) 9h = 2.93dB (typical) Ah = 3.13dB (typical) Bh = 3.35dB (typical) Ch = 3.53dB (typical) Dh = 3.72dB (typical) Eh = 3.89dB (typical) Fh = 4.07dB (typical)

10.1.21 INT_STATUS_1 Register (Offset = A3h) [Reset = 00h]

INT_STATUS_1 is shown in Table 10-23.

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Table 10-23 INT_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_GPIO1_RISING_EDGE	R/W1C	0h	GPIO1 Rising Edge enable 0h = No Interrupt 1h = Interrupt
6	INT_GPIO1_FALLING_EDGE	R/W1C	0h	GPIO1 Falling Edge enable 0h = No Interrupt 1h = Interrupt
5	INT_GPIO0_RISING_EDGE	R/W1C	0h	GPIO0 Rising Edge enable 0h = No Interrupt 1h = Interrupt
4	INT_GPIO0_FALLING_EDGE	R/W1C	0h	GPIO0 Falling Edge enable 0h = No Interrupt 1h = Interrupt
3	INT_USB_REMOTE_WAKE_P1	R/W1C	0h	Remote Wake Event Detect on USB Port 1 0h = No Interrupt 1h = Interrupt
2	INT_USB_DISCONNECT_P1	R/W1C	0h	Disconnect event has occurred on Port 1 0h = No Interrupt 1h = Interrupt
1	INT_USB_REMOTE_WAKE_P0	R/W1C	0h	Remote Wake Event Detect on USB Port 0 0h = No Interrupt 1h = Interrupt
0	INT_USB_DISCONNECT_P0	R/W1C	0h	Disconnect event has occurred on Port 0 0h = No Interrupt 1h = Interrupt

10.1.22 INT_STATUS_2 Register (Offset = A4h) [Reset = 00h]

INT_STATUS_2 is shown in Table 10-24.

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Table 10-24 INT_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	INT_USB_DET_ATTACH_P1	R/W1C	0h	Device Attach event has occurred on Port 1 0h = No Interrupt 1h = Interrupt
2	INT_USB_DET_ATTACH_P0	R/W1C	0h	Device Attach event has occurred on Port 0 0h = No Interrupt 1h = Interrupt
1	INT_USB_OVP_P1	R/W1C	0h	Over voltage condition (DP/DN voltage > V_{OVP_TH}) has occurred port 1 0h = No Interrupt 1h = Interrupt
0	INT_USB_OVP_P0	R/W1C	0h	Over voltage condition (DP/DN voltage > V_{OVP_TH}) has occurred port 0 0h = No Interrupt 1h = Interrupt

10.1.23 REV_ID Register (Offset = B0h) [Reset = 03h]

REV_ID is shown in Table 10-25.

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Table 10-25 REV_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	REV_ID	RH	3h	Device revision. 4h = Device Revision 4

10.1.24 GLOBAL_CONFIG Register (Offset = B2h) [Reset = 00h]

GLOBAL_CONFIG is shown in Table 10-26.

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Table 10-26 GLOBAL_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SOFT_RST	WtoPH	0h	Writing a 1 to this field is equivalent to pulsing RESETB low
6	DISABLE_P1	R/W	0h	DIsabled Mode Repeater 1 (I2C will remain Active) (If port is not disconnected, wait until disconnect event to disable the repeater) 0h = Repeater Enabled 1h = Repeater Disabled
5	DISABLE_P0	R/W	0h	Disabled Mode Repeater 0 (I2C will remain Active) (If port is not disconnected, wait until disconnect event to disable the repeater) 0h = Repeater Enabled 1h = Repeater Disabled
4	INT_OUT_TYPE	R/W	0h	INT Output Type INT output drive strength in open drain mode will be the same as GPIO setting 0h = Open Drain 1h = push pull
3	INT_POLARITY	R/W	0h	INT pin polarity in push-pull mode only (open drain mode will always be Active low) 0h = Active High (only for push-pull) 1h = Active Low (only for push-pull, open drain will always be active low)
2	RESERVED	R/W	0h	Reserved
1-0	RESERVED	R	0h	Reserved

10.1.25 INT_ENABLE_1 Register (Offset = B3h) [Reset = 00h]

INT_ENABLE_1 is shown in Table 10-27.

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Table 10-27 INT_ENABLE_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO1_RISING_EDGE	R/W	0h	INT_GPIO1_RISING_EDGE enable. When GPIO1_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt on Rising Edge of GPIO1. When GPIO1_IN_TRIGGER_TYPE = 1 (Level), this enables Interrupt when GPIO1 = High. 0h = Not Enabled 1h = Enabled
6	GPIO1_FALLING_EDGE	R/W	0h	INT_GPIO1_FALLING_EDGE enable. When GPIO1_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt on Falling Edge of GPIO1. When GPIO1_IN_TRIGGER_TYPE = 1 (Level), this enables Interrupt when GPIO1 = Low. 0h = Not Enabled 1h = Enabled
5	GPIO0_RISING_EDGE	R/W	0h	INT_GPIO0_RISING_EDGE enable. When GPIO0_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt on Rising Edge of GPIO0. When GPIO0_IN_TRIGGER_TYPE = 1 (Level), this enables Interrupt when GPIO0 = High. 0h = Not Enabled 1h = Enabled
4	GPIO0_FALLING_EDGE	R/W	0h	INT_GPIO0_FALLING_EDGE enable. When GPIO0_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt on Falling Edge of GPIO0. When GPIO0_IN_TRIGGER_TYPE = 1 (Level), this enables Interrupt when GPIO0 = Low. 0h = Not Enabled 1h = Enabled
3	USB_REMOTE_WAKE_P1	R/W	0h	INT_USB_REMOTE_WAKE_P1 enable. See L2 State Interrupt Modes 0h = Not Enabled 1h = Enabled
2	USB_DISCONNECT_P1	R/W	0h	INT_USB_DISCONNECT_P1 enable. See L2 State Interrupt Modes 0h = Not Enabled 1h = Enabled
1	USB_REMOTE_WAKE_P0	R/W	0h	INT_USB_REMOTE_WAKE_P0 enable. See L2 State Interrupt Modes 0h = Not Enabled 1h = Enabled
0	USB_DISCONNECT_P0	R/W	0h	INT_USB_DISCONNECT_P0 enable. See L2 State Interrupt Modes 0h = Not Enabled 1h = Enabled

10.1.26 INT_ENABLE_2 Register (Offset = B4h) [Reset = 00h]

INT_ENABLE_2 is shown in Table 10-28.

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Table 10-28 INT_ENABLE_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_OVERRIDE_EN	R/W	0h	INT pin enable 0h = Not Enabled 1h = Enabled
6	INT_VALUE	R/W	0h	Value to drive on INT when INT_OVERRIDE=1 INT output pin will indicate the interrupt assertion. It will follow the INT pin configuration. In open drain mode it will be active low to indicate interrupt assertion and in push-pull mode it will follow active low/high configuration to indicate INT assertion. 0h = output : interrupt not asserted 1h = output : interrupt asserted
5-4	RESERVED	R	0h	Reserved
3	USB_DETECT_ATTACH_P1	R/W	0h	INT_USB_DET_ATTACH_P1 enable. Enable device attach detection while eDSP is powered down 0h = Not Enabled 1h = Enabled
2	USB_DETECT_ATTACH_P0	R/W	0h	INT_USB_DET_ATTACH_P0 enable. Enable device attach detection while eDSP is powered down 0h = Not Enabled 1h = Enabled
1	USB_OVP_P1	R/W	0h	Over Voltage Port 1 interrupt enable 0h = Not Enabled 1h = Enabled
0	USB_OVP_P0	R/W	0h	Over Voltage Port 0 interrupt enable 0h = Not Enabled 1h = Enabled