SNLS757 June   2024 TUSB2E221

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Variants
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  8. 7 Parametric Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 2.0
      2. 8.3.2 eUSB2
      3. 8.3.3 Cross MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power-Down Mode
      3. 8.4.3  UART Mode
      4. 8.4.4  Auto-Resume ECR
      5. 8.4.5  L2 State Interrupt Modes
      6. 8.4.6  Attach Detect Interrupt Mode
      7. 8.4.7  GPIO Mode
        1. 8.4.7.1 EQ0 as GPIO0
        2. 8.4.7.2 EQ1 as GPIO1
        3. 8.4.7.3 EQ2/INT as GPIO2
      8. 8.4.8  CROSS
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Target Interface
      2. 8.5.2 Register Access Protocol (RAP)
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Dual Port System
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 eUSB PHY Settings Recommendation
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Reset
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Example Layout
  11. 10Register Map
    1. 10.1 TUSB2E221 Registers
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1 I2C Target Interface

I2C target interface enables access to internal registers by the system application processor. The primary function of the interface is to enable configuring various PHY parameters, controlling the GPIO pins, and enabling USB-BC functions. The TUSB2E221 repeater functions operates after power up without requiring I2C configuration.

The TUSB2E221 has I2C 7-bit target address of 0x4F. 8-bit address of Write: 0x9E and Read: 0x9F.

I2C default target address can be changed at the factory through one-time programming.

I2C drive strength can be changed through the I2C.

Table 8-5 Recommended I2C Drive Strength for I2C Bus Speed, Bus Pullup and Bus Capacitance
I2C FM+ (1MHz Max)I2C drive strength (IOL) selection
I2C bus pullup RPU
C(bus) pF1kΩ2.2kΩ4kΩ7kΩ
10-50≅8mA≅4mAN/AN/A
10-90≅8mAN/AN/AN/A
10-150N/AN/AN/AN/A
10-200N/AN/AN/AN/A
I2C FM (400kHz Max)I2C drive strength (IOL) selection
I2C bus pullup RPU
C(bus) pF1kΩ2.2kΩ4kΩ7kΩ
10-50≅8mA≅4mA≅2mAN/A
10-90≅8mA≅4mAN/AN/A
10-150≅8mA≅8mAN/AN/A
10-200≅8mAN/AN/AN/A
I2C STD (100kHz Max)I2C drive strength (IOL) selection
I2C bus pullup RPU
C(bus) pF1kΩ2.2kΩ4kΩ7kΩ
10-50≅8mA≅4mA≅2mA≅1mA
10-90≅8mA≅4mA≅2mA≅1mA
10-150≅8mA≅4mA≅2mA≅2mA
10-200≅8mA≅4mA≅2mA≅2mA
TUSB2E221 I2C Write with DataFigure 8-5 I2C Write with Data

Use this procedure to write data to TUSB2E221 I2C registers (refer to Figure 8-5):

  1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E221 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB2E221 acknowledges the address cycle.
  3. The host presents the register offset within the TUSB2E221 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB2E221 acknowledges the sub-address cycle.
  5. The host presents the first byte of data to be written to the I2C register.
  6. The TUSB2E221 acknowledges the byte transfer.
  7. The host may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB2E221.
  8. The host terminates the write operation by generating a stop condition (P).

TUSB2E221 I2C Read Without Repeated StartFigure 8-6 I2C Read Without Repeated Start

Use this procedure to read the TUSB2E221 I2C registers without a repeated Start (refer Figure 8-6).

  1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E221 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
  2. The TUSB2E221 acknowledges the 7-bit address cycle.
  3. Following the acknowledge the host continues sending clock.
  4. The TUSB2E221 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB2E221 shall start at the register offset specified in the write.
  5. The TUSB2E221 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after each byte transfer; the I2C host acknowledges reception of each data byte transfer.
  6. If an ACK is received, the TUSB2E221 transmits the next byte of data as long as host provides the clock. If a NAK is received, the TUSB2E221 stops providing data and waits for a stop condition (P).
  7. The host terminates the write operation by generating a stop condition (P).

TUSB2E221 I2C Read with Repeated StartFigure 8-7 I2C Read with Repeated Start

Use this procedure to read the TUSB2E221 I2C registers with a repeated Start (refer Figure 8-7).

  1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E221 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB2E221 acknowledges the 7-bit address cycle.
  3. The host presents the register offset within the TUSB2E221 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB2E221 acknowledges the register offset cycle.
  5. The host presents a repeated start condition (Sr).
  6. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E221 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  7. The TUSB2E221 acknowledges the 7-bit address cycle.
  8. The TUSB2E221 transmit the contents of the memory registers MSB-first starting at the register offset.
  9. The TUSB2E221 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after each byte transfer; the I2C host acknowledges reception of each data byte transfer.
  10. If an ACK is received, the TUSB2E221 transmits the next byte of data as long as host provides the clock. If a NAK is received, the TUSB2E221 stops providing data and waits for a stop condition (P).
  11. The host terminates the read operation by generating a stop condition (P).

TUSB2E221 I2C Write Without DataFigure 8-8 I2C Write Without Data

Use this procedure to set a starting sub-address for I2C reads (refer to Figure 8-8).

  1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E221 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB2E221 acknowledges the address cycle.
  3. The host presents the register offset within the TUSB2E221 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB2E221 acknowledges the register offset cycle.
  5. The host terminates the write operation by generating a stop condition (P).

Note: After initial power-up, if no register offset is included for the read procedure (refer to Figure 8-6), then reads start at register offset 00h and continue byte by byte through the registers until the I2C host terminates the read operation. During a read operation, the TUSB2E221 auto-increments the I2C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C host.
TUSB2E221 I2C Timing DiagramFigure 8-9 I2C Timing Diagram