SNLS757 June   2024 TUSB2E221

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Variants
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  8. 7 Parametric Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 2.0
      2. 8.3.2 eUSB2
      3. 8.3.3 Cross MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power-Down Mode
      3. 8.4.3  UART Mode
      4. 8.4.4  Auto-Resume ECR
      5. 8.4.5  L2 State Interrupt Modes
      6. 8.4.6  Attach Detect Interrupt Mode
      7. 8.4.7  GPIO Mode
        1. 8.4.7.1 EQ0 as GPIO0
        2. 8.4.7.2 EQ1 as GPIO1
        3. 8.4.7.3 EQ2/INT as GPIO2
      8. 8.4.8  CROSS
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Target Interface
      2. 8.5.2 Register Access Protocol (RAP)
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Dual Port System
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 eUSB PHY Settings Recommendation
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Reset
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Example Layout
  11. 10Register Map
    1. 10.1 TUSB2E221 Registers
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

TUSB2E221 YCG Package, 25-Pin DSBGA (Top View)Figure 5-1 YCG Package, 25-Pin DSBGA (Top View)
TUSB2E221 VBW Package20-Pin WQFN#GUID-5026D859-2D29-4122-BDDB-BFF91112254A/GUID-8C65C117-0515-460A-B662-43C55B7841E6(Top View) Figure 5-2 VBW Package20-Pin WQFN(1)(Top View)
Table 5-1 Pin Functions
PIN I/O RESET STATE ASSOCIATED ESD SUPPLY DESCRIPTION
NAME VBW(1) YCG
CROSS – C2 Digital Input N/A VDD3V3 Indicates mux orientation. Used to specify orientation of internal Crossbar switch
CROSS = Low: eUSB0 «–» USBA and eUSB1 «–» USBB
CROSS = High: eUSB0 «–» USBB and eUSB1«–» USBA
Sampled at deassertion of RESETB
DNA 9 B5 Analog I/O Hi-Z VDD3V3 USB port A D- pin
DPA 10 A5 Analog I/O Hi-Z VDD3V3 USB port A D+ pin
DNB 7 D5 Analog I/O Hi-Z VDD3V3 USB port B D- pin
DPB 6 E5 Analog I/O Hi-Z VDD3V3 USB port B D+ pin
eDN0 17 B1 Analog I/O Hi-Z VDD1V8 eUSB2 port 0 D- pin
eDP0 16 A1 Analog I/O Hi-Z VDD1V8 eUSB2 port 0 D+ pin
eDN1 19 D1 Analog I/O Hi-Z VDD1V8 eUSB2 port 1 D- pin
eDP1 20 E1 Analog I/O Hi-Z VDD1V8 eUSB2 port 1 D+ pin
EQ0 2 E2 Digital I/O Internal pulldown 1MΩ typical (disabled after reset)


VDD3V3


 (See Table 5-2)
EQ1 4 E3 Digital I/O Internal pulldown 1MΩ typical (disabled after reset)


VDD3V3


 (See Table 5-2)
EQ2/INT 12 A4 Digital I/O Internal pulldown 1MΩ typical (disabled after reset) VDD3V3 I2C Mode: Open Drain active low level sensitive interrupt output to system
non-I2C Mode: (See Table 5-2)
GND 8 B3 GND N/A N/A GND
C1
C4
18 C5
D3
RESETB 5 E4 Digital Input N/A VDD1V8 Active Low Reset. After the RESETB deassertion, both repeaters will be enabled and be in eUSB2 default mode awaiting configuration from eDSPr or eUSPr.
SCL 13 A3 Digital I/O Internal pulldown 1MΩ typical (disabled after reset) VDD3V3 I2 clockOpen drain I/O. Device Mode Matrix (See Table 5-2) SCL SDA Mode
Low Low Non-I2C USB Repeater (See Table 5-3)
Low High Non-I2C USB Repeater (See Table 5-3) BC 1.2 CDP advertising enabled in host mode
SDA 14 A2 Digital I/O Internal pulldown 1MΩ typical (disabled after reset) VDD3V3 Bidirectional I2C data. Open drain I/O. Pulled up to I2C rail through an external resistor High Low Non-I2C USB Repeater (See Table 5-5)
High High I2C Enabled
VDD1V8 11 B4 PWR N/A N/A 1.8V analog supply voltage
D4
VDD3V3 1 B2 PWR N/A N/A 3.3V supply voltage
15 D2
VIOSEL 3 C3 Digital Input N/A VDD3V3 VIOSEL is used to select digital I/O input voltage for GPIOs, CROSS and I2C
VIOSEL = VSS sets device into 1.2V I/O mode
VIOSEL = VDD1V8 sets device into 1.8V I/O mode
VIOSEL pin is real time control and not only latched at powered on reset. Be careful when this pin changes dynamically after power-on-reset because the output voltage may change from 1.2V to 1.8V.
(1) The VBW (WQFN) package is preview only.
Table 5-2 Device Mode Configuration
SCL SDA EQ0 EQ1 EQ2 eUSB0 eUSB1 I2C Interface USBA and USBB CDP advertising in host mode
Low/Float Low/Float USB2 PHY Configuration USB repeater USB repeater Disabled Disabled
Low/Float High USB2 PHY Configuration USB repeater USB repeater Disabled Enabled
High Low/Float eUSB PHY Configuration High-Z USB repeater USB repeater Disabled Disabled
High High Low/Float Low/Float INT interrupt output USB repeater USB repeater Enabled Per register
High High High Low/Float INT interrupt output Carkit UART bypass USB repeater Enabled Per register
High High Low/Float High INT interrupt output USB repeater Carkit UART bypass Enabled Per register
High High High High INT interrupt output Carkit UART bypass Carkit UART bypass Enabled Per register

The eUSB phy configurations used Table 5-3 assumes the channel between the device and host is 5 inches FR4.

Table 5-3 USB2 PHY Configuration
EQ0 EQ1 EQ2 USB2 PHY
Compensation Level		 eUSB0/1 channel USB ESR(1)
(Ω)
Low/Float Low/Float Low/Float Level 0 5 inches FR4

USB A: 2.5

USB B: 2.5
High Low/Float Low/Float Level 1 5 inches FR4

USB A: 10

USB B: 10
Low/Float High Low/Float Level 2 5 inches FR4

USB A: 17.5

USB B: 17.5
High High Low/Float Level 3 5 inches FR4

USB A: 10

USB B: 17.5
Low/Float Low/Float High Level 4 5 inches FR4

USB A: 2.5

USB B: 10
High Low/Float High Level 5 5 inches FR4

USB A: 10

USB B: 2.5
Low/Float High High Level 6 5 inches FR4

USB A: 17.5

USB B: 2.5
High High High Level 7 5 inches FR4

USB A: 2.5

USB B: 17.5
(1) Equivalent series resistance (ESR) is the combination of any resistance between the device and the USB connector such as switches, multipliexers, just to name a few.
Table 5-4 USB2 PHY Compensation Levels
USB2 PHY Compensation Levels
Register Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
E_EQ_Px Register Default Register Default Register Default Register Default Register Default Register Default Register Default Register Default
E_HS_TX_AMPLITUDE_Px Register Default Register Default Register Default Register Default Register Default Register Default Register Default Register Default
E_HS_TX_PRE_EMPHASIS_Px Register Default Register Default Register Default Register Default Register Default Register Default Register Default Register Default
U_EQ_Px

USB A: 0x0

USB B: 0x0

USB A: 0x2

USB B: 0x2

USB A: 0x5

USB B: 0x5

USB A: 0x5

USB B: 0x2

USB A: 0x2

USB B: 0x0

USB A: 0x0

USB B: 0x2

USB A: 0x0

USB B: 0x5

USB A: 0x5

USB B: 0x0
U_SQUELCH_THRESHOLD_Px

USB A: 0x4

USB B: 0x4

USB A: 0x5

USB B: 0x5

USB A: 0x6

USB B: 0x6

USB A: 0x6

USB B: 0x5

USB A: 0x5

USB B: 0x4

USB A: 0x4

USB B: 0x5

USB A: 0x4

USB B: 0x6

USB A: 0x6

USB B: 0x4
U_DISCONNECT_THRESHOLD_Px

USB A: 0x5

USB B: 0x5

USB A: 0x8

USB B: 0x8

USB A: 0x8

USB B: 0x8

USB A: 0x8

USB B: 0x8

USB A: 0x8

USB B: 0x5

USB A: 0x5

USB B: 0x8

USB A: 0x5

USB B: 0x8

USB A: 0x8

USB B: 0x5
U_HS_TX_AMPLITUDE_Px

USB A: 0x5

USB B: 0x5

USB A: 0x9

USB B: 0x9

USB A: 0xD

USB B: 0xD

USB A: 0xD

USB B: 0x9

USB A: 0x9

USB B: 0x5

USB A: 0x5

USB B: 0x9

USB A: 0x5

USB B: 0xD

USB A: 0xD

USB B: 0x5
U_HS_TX_PRE_EMPHASIS_Px

USB A: 0x0

USB B: 0x0

USB A: 0x1

USB B: 0x1

USB A: 0x3

USB B: 0x3

USB A: 0x3

USB B: 0x1

USB A: 0x1

USB B: 0x0

USB A: 0x0

USB B: 0x1

USB A: 0x0

USB B: 0x3

USB A: 0x3

USB B: 0x0
Table 5-5 eUSB PHY Configuration
EQ0 EQ1 EQ2 eUSB PHY
Compensation Level		 eUSB0 ESR(1)
(Ω) 		eUSB1 ESR (1)
(Ω) 		USBA (DPA/DNA) ESR (1)
(Ω)		 USBB (DPB/DNB) ESR (1)
(Ω)
Low/Float Low/Float Low/Float Level 0 2.5 2.5 2.5 2.5
High Low/Float Low/Float Level 1 7.5 7.5 2.5 2.5
Low/Float High Low/Float Level 2 15 15 2.5 2.5
High High Low/Float Level 3 25 25 2.5 2.5
(1) Equivalent series resistance (ESR) is the combination of any resistance between the device and the USB connector or between device and the SOC such as switches, multipliexers, just to name a few.
Table 5-6 eUSB PHY Compensation Levels
eUSB PHY Compensation Levels
Register Level 0 Level 1 Level 2 Level 3
E_EQ_Px 0x1 0x3 0x7 0x10
E_HS_TX_AMPLITUDE_Px 0x3 0x3 0x5 0x7
E_HS_TX_PRE_EMPHASIS_Px 0x1 0x2 0x4 0x6
U_EQ_Px Register Default Register Default Register Default Register Default
U_SQUELCH_THRESHOLD_Px Register Default Register Default Register Default Register Default
U_DISCONNECT_THRESHOLD_Px Register Default Register Default Register Default Register Default
U_HS_TX_AMPLITUDE_Px Register Default Register Default Register Default Register Default
U_HS_TX_PRE_EMPHASIS_Px Register Default Register Default Register Default Register Default