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  • TUSB3410 USB to Serial Port Controller

    • SLLS519J March   2002  – July 2017 TUSB3410

      PRODUCTION DATA.  

  • CONTENTS
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  • TUSB3410 USB to Serial Port Controller
  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagrams
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing and Switching Characteristics Information
      1. 4.6.1 Wakeup Timing (WAKEUP or RI/CP Transitions)
      2. 4.6.2 Reset Timing
    7. 4.7 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Device Functional Modes
      1. 5.3.1 USB Interface Configuration
        1. 5.3.1.1 External Memory Case
        2. 5.3.1.2 Host Download Case
      2. 5.3.2 USB Data Movement
      3. 5.3.3 Serial Port Setup
      4. 5.3.4 Serial Port Data Modes
        1. 5.3.4.1 RS-232 Data Mode
        2. 5.3.4.2 RS-485 Data Mode
        3. 5.3.4.3 IrDA Data Mode
    4. 5.4 Processor Subsystems
      1. 5.4.1 DMA Controller
        1. 5.4.1.1 Bulk Data I/O Using the EDB
          1. 5.4.1.1.1 IN Transaction (TUSB3410 to Host)
          2. 5.4.1.1.2 OUT Transaction (Host to TUSB3410)
      2. 5.4.2 UART
        1. 5.4.2.1 UART Data Transfer
          1. 5.4.2.1.1 Receiver Data Flow
          2. 5.4.2.1.2 Hardware Flow Control
          3. 5.4.2.1.3 Auto RTS (Receiver Control)
          4. 5.4.2.1.4 Auto CTS (Transmitter Control)
          5. 5.4.2.1.5 Xon/Xoff Receiver Flow Control
          6. 5.4.2.1.6 Xon/Xoff Transmit Flow Control
      3. 5.4.3 I2C Port
        1. 5.4.3.1 Random-Read Operation
          1. 5.4.3.1.1 Device Address + EPROM [High Byte]
          2. 5.4.3.1.2 EPROM [Low Byte]
        2. 5.4.3.2 Current-Address Read Operation
        3. 5.4.3.3 Sequential-Read Operation
          1. 5.4.3.3.1 Device Address
          2. 5.4.3.3.2 N-Byte Read (31 Bytes)
          3. 5.4.3.3.3 Last-Byte Read (Byte 32)
        4. 5.4.3.4 Byte-Write Operation
          1. 5.4.3.4.1 Device Address + EPROM [High Byte]
          2. 5.4.3.4.2 EPROM [Low Byte]
          3. 5.4.3.4.3 EPROM [DATA]
        5. 5.4.3.5 Page-Write Operation
          1. 5.4.3.5.1 Device Address + EPROM [High Byte]
          2. 5.4.3.5.2 EPROM [Low Byte]
          3. 5.4.3.5.3 EPROM [DATA]—31 Bytes
          4. 5.4.3.5.4 EPROM [DATA]—Last Byte
    5. 5.5 Memory
      1. 5.5.1  MCU Memory Map
      2. 5.5.2  Registers
        1. 5.5.2.1 Miscellaneous Registers
          1. 5.5.2.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h)
          2. 5.5.2.1.2 Boot Operation (MCU Firmware Loading)
          3. 5.5.2.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h)
      3. 5.5.3  Buffers + I/O RAM Map
      4. 5.5.4  Endpoint Descriptor Block (EDB−1 to EDB−3)
        1. 5.5.4.1  OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Base Addr: FF08h, FF10h, FF18h)
        2. 5.5.4.2  OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)
        3. 5.5.4.3  OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2)
        4. 5.5.4.4  OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)
        5. 5.5.4.5  OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)
        6. 5.5.4.6  OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)
        7. 5.5.4.7  IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Base Addr: FF48h, FF50h, FF58h)
        8. 5.5.4.8  IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)
        9. 5.5.4.9  IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2)
        10. 5.5.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)
        11. 5.5.4.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)
        12. 5.5.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)
        13. 5.5.4.13 Endpoint-0 Descriptor Registers
          1. 5.5.4.13.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h)
          2. 5.5.4.13.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h)
          3. 5.5.4.13.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h)
          4. 5.5.4.13.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h)
      5. 5.5.5  USB Registers
        1. 5.5.5.1  FUNADR: Function Address Register (Addr:FFFFh)
        2. 5.5.5.2  USBSTA: USB Status Register (Addr:FFFEh)
        3. 5.5.5.3  USBMSK: USB Interrupt Mask Register (Addr:FFFDh)
        4. 5.5.5.4  USBCTL: USB Control Register (Addr:FFFCh)
        5. 5.5.5.5  MODECNFG: Mode Configuration Register (Addr:FFFBh)
        6. 5.5.5.6  Clock Output Control
        7. 5.5.5.7  Vendor ID/Product ID
        8. 5.5.5.8  SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh)
        9. 5.5.5.9  SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh)
        10. 5.5.5.10 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh)
        11. 5.5.5.11 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh)
        12. 5.5.5.12 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh)
        13. 5.5.5.13 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh)
        14. 5.5.5.14 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h)
        15. 5.5.5.15 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h)
        16. 5.5.5.16 Function Reset and Power-Up Reset Interconnect
        17. 5.5.5.17 Pullup Resistor Connect and Disconnect
      6. 5.5.6  DMA Controller Registers
        1. 5.5.6.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0h)
        2. 5.5.6.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel) (Addr:FFE1h)
        3. 5.5.6.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel) (Addr:FFE4h)
        4. 5.5.6.4 DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5h)
      7. 5.5.7  UART Registers
        1. 5.5.7.1  RDR: Receiver Data Register (Addr:FFA0h)
        2. 5.5.7.2  TDR: Transmitter Data Register (Addr:FFA1h)
        3. 5.5.7.3  LCR: Line Control Register (Addr:FFA2h)
        4. 5.5.7.4  FCRL: UART Flow Control Register (Addr:FFA3h)
        5. 5.5.7.5  Transmitter Flow Control
        6. 5.5.7.6  MCR: Modem-Control Register (Addr:FFA4h)
        7. 5.5.7.7  LSR: Line-Status Register (Addr:FFA5h)
        8. 5.5.7.8  MSR: Modem-Status Register (Addr:FFA6h)
        9. 5.5.7.9  DLL: Divisor Register Low Byte (Addr:FFA7h)
        10. 5.5.7.10 DLH: Divisor Register High Byte (Addr:FFA8h)
        11. 5.5.7.11 Baud-Rate Calculation
        12. 5.5.7.12 XON: Xon Register (Addr:FFA9h)
        13. 5.5.7.13 XOFF: Xoff Register (Addr:FFAAh)
        14. 5.5.7.14 MASK: UART Interrupt-Mask Register (Addr:FFABh)
      8. 5.5.8  Expanded GPIO Port
        1. 5.5.8.1 Input/Output and Control Registers
          1. 5.5.8.1.1 PUR_3: GPIO Pullup Register for Port 3 (Addr:FF9Eh)
      9. 5.5.9  Interrupts
        1. 5.5.9.1 8052 Interrupt and Status Registers
          1. 5.5.9.1.1 8052 Standard Interrupt Enable (SIE) Register
          2. 5.5.9.1.2 Additional Interrupt Sources
          3. 5.5.9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h)
          4. 5.5.9.1.4 Logical Interrupt Connection Diagram (Internal/External)
      10. 5.5.10 I2C Registers
        1. 5.5.10.1 I2CSTA: I2C Status and Control Register (Addr:FFF0h)
        2. 5.5.10.2 I2CADR: I2C Address Register (Addr:FFF3h)
        3. 5.5.10.3 I2CDAI: I2C Data-Input Register (Addr:FFF2h)
        4. 5.5.10.4 I2CDAO: I2C Data-Output Register (Addr:FFF1h)
    6. 5.6 Boot Modes
      1. 5.6.1  Introduction
      2. 5.6.2  Bootcode Programming Flow
      3. 5.6.3  Default Bootcode Settings
        1. 5.6.3.1 Device Descriptor
        2. 5.6.3.2 Configuration Descriptor
        3. 5.6.3.3 Interface Descriptor
        4. 5.6.3.4 Endpoint Descriptor
        5. 5.6.3.5 String Descriptor
      4. 5.6.4  External I2C Device Header Format
        1. 5.6.4.1 Product Signature
        2. 5.6.4.2 Descriptor Block
          1. 5.6.4.2.1 Descriptor Prefix
          2. 5.6.4.2.2 Descriptor Content
      5. 5.6.5  Checksum in Descriptor Block
      6. 5.6.6  Header Examples
        1. 5.6.6.1 TUSB3410 Bootcode Supported Descriptor Block
        2. 5.6.6.2 USB Descriptor Header
        3. 5.6.6.3 Autoexec Binary Firmware
      7. 5.6.7  USB Host Driver Downloading Header Format
      8. 5.6.8  Built-In Vendor Specific USB Requests
        1. 5.6.8.1 Reboot
        2. 5.6.8.2 Force Execute Firmware
        3. 5.6.8.3 External Memory Read
        4. 5.6.8.4 External Memory Write
        5. 5.6.8.5 I2C Memory Read
        6. 5.6.8.6 I2C Memory Write
        7. 5.6.8.7 Internal ROM Memory Read
      9. 5.6.9  Bootcode Programming Consideration
        1. 5.6.9.1 USB Requests
          1. 5.6.9.1.1 USB Request Transfers
          2. 5.6.9.1.2 Interrupt Handling Routine
        2. 5.6.9.2 Hardware Reset Introduced by the Firmware
      10. 5.6.10 File Listings
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Upstream Port Implementation
        2. 6.2.2.2 Crystal Implementation
        3. 6.2.2.3 RS-232 Implementation
        4. 6.2.2.4 TUSB3410 Power Implementation
      3. 6.2.3 Application Performance Plot
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Differential Signal Spacing
      3. 6.3.3 Differential Signal Rules
      4. 6.3.4 Layout Example
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 Digital Supplies 3.3 V
      2. 6.4.2 Digital Supplies 1.8 V
    5. 6.5 Crystal Selection
    6. 6.6 External Circuit Required for Reliable Bus Powered Suspend Operation
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Related Links
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information
  9. IMPORTANT NOTICE

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DATA SHEET

TUSB3410 USB to Serial Port Controller

1 Device Overview

1.1 Features

  • Fully Compliant With USB 2.0 Full-Speed Specifications: TID#40340262
  • Supports 12-Mbps USB Data Rate (Full Speed)
  • Supports USB Suspend, Resume, and Remote Wake-Up Operations
  • Configurable to Bus-Powered and Self-Powered Operation
  • Supports a Total of Three Input and Three Output (Interrupt, Bulk) Endpoints
  • Integrated 8052 Microcontroller With:
    • 256 × 8 RAM for Internal Data
    • 10K × 8 ROM (With USB and I2C Bootloader)
    • 16K × 8 RAM for Code Space Loadable From Host or I2C Port
    • 2K × 8 Shared RAM Used for Data Buffers and Endpoint Descriptor Blocks (EDBs)
    • Master I2C Controller for EEPROM Device Access
    • MCU Operates at 24 MHz, Providing 2-MIPS Operation
    • 128-ms Watchdog Timer
  • Enhanced UART Features:
    • Software and Hardware Flow Control
    • Automatic RS-485 Bus Transceiver Control, With and Without Echo
    • Selectable IrDA Mode for Up to 115.2-kbps Transfer
    • Software-Selectable Baud Rate From 50 BPS to 921.6 kbps
    • Programmable Serial-Interface Characteristics
      • 5-, 6-, 7-, or 8-Bit Characters
      • Even, Odd, or No Parity-bit Generation and Detection
      • 1-, 1.5-, or 2-Stop Bit Generation
    • Line Break Generation and Detection
    • Internal Test and Loopback Capabilities
    • Modem Control Functions (CTS, RTS, DSR, RI and DCD)
    • Internal Diagnostic Capability
      • Loopback Control for Communications
        Link-Fault Isolation
      • Break, Parity, Overrun, Framing-Error Simulation

1.2 Applications

  • Modems
  • Peripherals:
    Printers, Handheld Devices, and so on
  • Medical Meters
  • DSP and µC Interface

1.3 Description

The TUSB3410 device provides bridging between a USB port and an enhanced UART serial port. The device contains an 8052 microcontroller unit (MCU) with 16KB of RAM that can be loaded from the host or from the external onboard memory through an I2C. The device also contains 10KB of ROM that allows the MCU to configure the USB port at boot time. The ROM code also contains an I2C bootloader. All device functions (such as the USB command decoding, UART setup, and error reporting) are managed by the internal MCU firmware in unison with the PC host.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
TUSB3410 VQFN (32) 5.00 mm × 5.00 mm
LQFP (32) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

1.4 Functional Block Diagram

TUSB3410 TUSB3410I fig001_2_lls519.gif

2 Revision History

Changes from I Revision (November 2015) to J Revision

  • Changed pin 21 From: DTR To: active low DTR in the Pin Functions tableGo
  • Changed the description of bit 7 CONT in USBCTL: USB Control Register (Addr:FFFCh), CONT= 0 From: enabled To: disables, CONT= 1 From: disbaled To: enabledGo

Changes from H Revision (April 2013) to I Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Deleted Ordering Information table.Go

3 Pin Configuration and Functions

3.1 Pin Diagrams

RHB Package
32-Pin VQFN
Top View

TUSB3410 TUSB3410I VF_pack_top_view_lls519.png

VF Package
32-Pin LQFP
Bottom View

TUSB3410 TUSB3410I RHB_pack_bot_view_lls519.png

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CLKOUT 22 O Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see (1) and Section 5.5.5.5)
CTS 13 I UART: Clear to send(4)
DCD 15 I UART: Data carrier detect(4)
DM 7 I/O Upstream USB port differential data minus
DP 6 I/O Upstream USB port differential data plus
DSR 14 I UART: Data set ready(4)
DTR 21 O UART: Data terminal ready(1)
GND 8, 18, 28 GND Digital ground
P3.0 32 I/O General-purpose I/O 0 (port 3, terminal 0)(3)(5)(8)
P3.1 31 I/O General-purpose I/O 1 (port 3, terminal 1)(3)(5)(8)
P3.3 30 I/O General-purpose I/O 3 (port 3, terminal 3)(3)(5)(8)
P3.4 29 I/O General-purpose I/O 4 (port 3, terminal 4)(3)(5)(8)
PUR 5 O Pullup resistor connection(2)
RESET 9 I Device master reset input(4)
RI/CP 16 I UART: Ring indicator(4)
RTS 20 O UART: Request to send(1)
SCL 11 O Master I2C controller: clock signal(1)
SDA 10 I/O Master I2C controller: data signal(1)(5)
SIN/IR_SIN 17 I UART: Serial input data / IR Serial data input(6)
SOUT/IR_SOUT 19 O UART: Serial output data / IR Serial data output(7)
SUSPEND 2 O Suspend indicator terminal(3). When this terminal is asserted high, the device is in suspend mode.
TEST0 23 I Test input (for factory test only). This terminal must be tied to VCC through a 10-kΩ resistor.
TEST1 24 I Test input (for factory test only)(5). This terminal must be tied to VCC through a 10-kΩ resistor.
VCC 3, 25 PWR 3.3 V
VDD18 4 PWR 1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is low. When VREGEN is high, 1.8 V must be supplied externally.
VREGEN 1 I This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator.
WAKEUP 12 I Remote wake-up request terminal. When low, wakes up system(5)
X1/CLKI 27 I 12-MHz crystal input or clock input
X2 26 O 12-MHz crystal output
(1) 3-state CMOS output (±4-mA drive and sink)
(2) 3-state CMOS output (±8-mA drive and sink)
(3) 3-state CMOS output (±12-mA drive and sink)
(4) TTL-compatible, hysteresis input
(5) TTL-compatible, hysteresis input, with internal 100-µA active pullup resistor
(6) TTL-compatible input without hysteresis, with internal 100-µA active pullup resistor
(7) Normal or IR mode: 3-state CMOS output (±4-mA drive and sink)
(8) The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the output is high impedance.

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage −0.5 3.6 V
VI Input voltage −0.5 VCC + 0.5 V
VO Output voltage −0.5 VCC + 0.5 V
IIK Input clamp current ±20 mA
IOK Output clamp current ±20 mA
Tstg Storage temperature Industrial –65 150 °C
Standard –55 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge (ESD) performance Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±2000 V
Charged Device Model (CDM),
per JESD22-C101(2)		 All pins ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VI Input voltage 0 VCC V
VIH High-level input voltage TTL 2 VCC V
CMOS 0.7 × VCC VCC
VIL Low-level input voltage TTL 0 0.8 V
CMOS 0 0.2 × VCC
TA Operating temperature Commercial range 0 70 °C
Industrial range –40 85 °C

4.4 Thermal Information

THERMAL METRIC(1) TUSB3410 UNIT
RHB (VQFN) VF (LQFP)
32 PINS
RθJA Junction-to-ambient thermal resistance 32.1 70.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.6 31.4 °C/W
RθJB Junction-to-board thermal resistance 6.5 28.3 °C/W
ψJT Junction-to-top characterization parameter 0.2 2.2 °C/W
ψJB Junction-to-board characterization parameter 6.5 28.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 24.6 31.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application report.

4.5 Electrical Characteristics

TA = 25°C, VCC = 3.3 V ±5%, VSS = 0 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage TTL IOH = –4 mA VCC – 0.5 V
CMOS VCC – 0.5
VOL Low-level output voltage TTL IOL = 4 mA 0.5 V
CMOS 0.5
VIT+ Positive threshold voltage TTL VI = VIH 1.8 V
CMOS 0.7 × VCC
VIT− Negative threshold voltage TTL VI = VIH 0.8 1.8 V
CMOS 0.2 × VCC
Vhys Hysteresis (VIT+ − VIT−) TTL VI = VIH 0.3 0.7 V
CMOS 0.17 × VCC 0.3 × VCC
IIH High-level input current TTL VI = VIH ±20 µA
CMOS ±1
IIL Low-level input current TTL VI = VIL ±20 µA
CMOS ±1
IOZ Output leakage current (Hi-Z) VI = VCC or VSS ±20 µA
IOL Output low drive current 0.1 mA
IOH Output high drive current 0.1 mA
ICC Supply current (operating) Serial data at 921.6 k 15 mA
Supply current (suspended) 200 µA
Clock duty cycle(1) 50%
Jitter specification(1) ±100 ppm
CI Input capacitance 18 pF
CO Output capacitance 10 pF
(1) Applies to all clock outputs

4.6 Timing and Switching Characteristics Information

4.6.1 Wakeup Timing (WAKEUP or RI/CP Transitions)

The TUSB3410 device can be brought out of the suspended state, or woken up, by a command from the host. The TUSB3410 device also supports remote wakeup and can be awakened by either of two input signals. A low pulse on the WAKEUP terminal or a low-to-high transition on the RI/CP terminal wakes up the device.

NOTE

For reliable operation, either condition must persist for approximately 3-ms minimum, which allows time for the crystal to power up because in the suspend mode, the crystal interface is powered down. The state of the WAKEUP or RI/CP terminal is then sampled by the clock to verify there was a valid wake-up event.

4.6.2 Reset Timing

There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μs. At power up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the reset signal exceeds 1.2 V. The second requirement is that the clock must be valid during the last 60 µs of the reset window. The third requirement is that, according to the USB specification, the device must be ready to respond to the host within 100 ms. This means that within the 100-ms window, the device must come out of reset, load any pertinent data from the I2C EEPROM device, and transfer execution to the application firmware if any is present. Because the latter two events can require significant time, the amount of which can change from system to system, TI recommends having the device come out of reset within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal must rise to
1.8 V within 30 ms.

These requirements are depicted in Figure 4-1. When using a 12-MHz crystal, the clock signal may take several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need to be elongated up to 10 ms or more to ensure that there is a 60-µs overlap with a valid clock.

TUSB3410 TUSB3410I fig013_3_lls519.gif Figure 4-1 Reset Timing

4.7 Typical Characteristics

TUSB3410 TUSB3410I C004_SLLS519.png
Figure 4-2 Supply Current at 3 V
TUSB3410 TUSB3410I C006_SLLS519.png
Figure 4-4 Supply Current at 3.6 V
TUSB3410 TUSB3410I C005_SLLS519.png
Figure 4-3 Supply Current at 3.3 V

 
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