JAJSF53E July   2015  – July 2024 TUSB4020BI

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings #GUID-E9510BAC-794F-43CD-A047-0D0FFB7C50BE/ABSMAXNOTE
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 3.3V I/O Electrical Characteristics
    6. 5.6 Hub Input Supply Current
    7. 5.7 Power-Up Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Battery Charging Features
      2. 6.3.2 USB Power Management
      3. 6.3.3 Clock Generation
      4. 6.3.4 Power-Up and Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 External Configuration Interface
    5. 6.5 Programming
      1. 6.5.1 One-Time Programmable (OTP) Configuration
      2. 6.5.2 I2C EEPROM Operation
      3. 6.5.3 SMBus Target Operation
    6. 6.6 Register Maps
      1. 6.6.1 Configuration Registers
        1. 6.6.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 6.6.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 6.6.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 6.6.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 6.6.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 6.6.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 6.6.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 6.6.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 6.6.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 6.6.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 6.6.1.11 Device Configuration Register 2 (offset = Ah)
        12. 6.6.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 6.6.1.13 Language ID LSB Register (offset = 20h)
        14. 6.6.1.14 Language ID MSB Register (offset = 21h)
        15. 6.6.1.15 Serial Number String Length Register (offset = 22h)
        16. 6.6.1.16 Manufacturer String Length Register (offset = 23h)
        17. 6.6.1.17 Product String Length Register (offset = 24h)
        18. 6.6.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 6.6.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 6.6.1.20 Product String Registers (offset = 90h to CFh)
        21. 6.6.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 6.6.1.22 Charging Port Control Register (offset = F2h)
        23. 6.6.1.23 Device Status and Command Register (offset = F8h)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Crystal Requirements
      2. 7.1.2 Input Clock Requirements
    2. 7.2 Typical Applications
      1. 7.2.1 Upstream Port Implementation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Downstream Port 1 Implementation
      3. 7.2.3 Downstream Port 2 Implementation
      4. 7.2.4 VBUS Power Switch Implementation
      5. 7.2.5 Clock, Reset, and Miscellaneous
      6. 7.2.6 Power Implementation
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply
      2. 7.3.2 Downstream Port Power
      3. 7.3.3 Ground
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Placement
        2. 7.4.1.2 Package Specific
        3. 7.4.1.3 Differential Pairs
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6.1.11 Device Configuration Register 2 (offset = Ah)

Figure 6-12 Register Offset Ah
76543210
00X00000
RRWRWRWRWRWRWR
LEGEND: R/W = Read/Write; R = Read only; –n = value after reset
Table 6-14 Bit Descriptions – Device Configuration Register 2
BitField NameAccessResetDescription
7RSVDROReserved. Read only, returns 0 when read.
6customBCfeaturesRWCustom Battery Charging Feature Enable. This bit controls the ability to write to the battery charging feature configuration controls.
0 = The HiCurAcpModeEn and AutoModeEnz bits are read only and the values are loaded from the OTP ROM.
1 = The HiCurAcpModeEn and AutoModeEnz bits are read/write and can be loaded by EEPROM or written by SMBus. from this register.
This bit can be written simultaneously with HiCurAcpModeEn and AutoModeEnz.
5pwrctlPolRWPower enable polarity. This bit is loaded at the deassertion of reset with the inverse value of the PWRCTL_POL terminal.
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
When the TUSB4020BI is in I2C mode, the TUSB4020BI loads this bit from the contents of the EEPROM.
When the TUSB4020BI is in SMBUS mode, the value can be overwritten by an SMBus host.
4HiCurAcpModeEnRO/RWHigh-current ACP mode enable. This bit enables the high-current tablet charging mode when the automatic battery charging mode is enabled for downstream ports.
0 = High current divider mode disabled
1 = High current divider mode enabled
This bit is read only unless the customBCfeatures bit is set to 1. Otherwise the value of this bit reflects the value of the OTP ROM HiCurAcpModeEn bit.
3RSVDRWReserved
2dsportEcrEnRWDSPort ECR enable. This bit enables full implementation of the DSPORT ECR (April 2013).
0 = DSPort ECR (April 2013) is enabled with the exception of changes related to the CCS bit is set upon entering U0, and changes related to avoiding or reporting compliance mode entry.
1 = The full DSport ECR (April 2013) is enabled.
1autoModeEnzRO/RWAutomatic Mode Enable. This bit is loaded from the OTP ROM.
The automatic mode only applies to downstream ports with battery charging enabled when the upstream port is not connected. Under these conditions:
0 = Automatic mode battery charging features are enabled. Only battery charging DCP and custom BC (divider mode) is enabled.
1 = Automatic mode is disabled; only battery charging DCP and CDP mode is supported.
Note: when the upstream port is connected, battery charging CDP mode is supported on all ports when this field is one.
This bit is read only unless the customBCfeatures bit is set to 1. Otherwise the value of this bit reflects the value of the OTP ROM AutoModeEnz bit.
0RSVDROReserved. Read only, returns 0 when read.