JAJSUV7C July   2015  – July 2024 TUSB4041I-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 3.3-V I/O Electrical Characteristics
    6. 5.6 Power-Up Timing Requirements
    7. 5.7 Hub Input Supply Current
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Battery Charging Features
      2. 6.3.2 USB Power Management
      3. 6.3.3 One-Time Programmable Configuration
      4. 6.3.4 Clock Generation
      5. 6.3.5 Crystal Requirements
      6. 6.3.6 Input Clock Requirements
      7. 6.3.7 Power-Up and Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 External Configuration Interface
      2. 6.4.2 I2C EEPROM Operation
      3. 6.4.3 SMBus Target Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Upstream Port Implementation
        2. 7.2.2.2 Downstream Port 1 Implementation
        3. 7.2.2.3 Downstream Port 2 Implementation
        4. 7.2.2.4 Downstream Port 3 Implementation
        5. 7.2.2.5 Downstream Port 4 Implementation
        6. 7.2.2.6 VBUS Power Switch Implementation
        7. 7.2.2.7 Clock, Reset, and Miscellaneous
        8. 7.2.2.8 TUSB4041I-Q1 Power Implementation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 TUSB4041I-Q1 Power Supply
      2. 7.3.2 Downstream Port Power
      3. 7.3.3 Ground
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Placement
        2. 7.4.1.2 Package Specific
        3. 7.4.1.3 Differential Pairs
      2. 7.4.2 Layout Example
  9. 8 Register Maps
    1. 8.1  Configuration Registers
    2. 8.2  ROM Signature Register
    3. 8.3  Vendor ID LSB Register
    4. 8.4  Vendor ID MSB Register
    5. 8.5  Product ID LSB Register
    6. 8.6  Product ID MSB Register
    7. 8.7  Device Configuration Register
    8. 8.8  Battery Charging Support Register
    9. 8.9  Device Removable Configuration Register
    10. 8.10 Port Used Configuration Register
    11. 8.11 Device Configuration Register 2
    12. 8.12 USB 2.0 Port Polarity Control Register
    13. 8.13 UUID Byte N Register
    14. 8.14 Language ID LSB Register
    15. 8.15 Language ID MSB Register
    16. 8.16 Serial Number String Length Register
    17. 8.17 Manufacturer String Length Register
    18. 8.18 Product String Length Register
    19. 8.19 Serial Number String Registers
    20. 8.20 Manufacturer String Registers
    21. 8.21 Product String Byte N Register
    22. 8.22 Additional Feature Configuration Register
    23. 8.23 Device Status and Command Register
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.11 Device Configuration Register 2

Offset = Ah

Figure 8-10 Device Configuration Register 2
76543210
RSVDcustomBCfeaturespwrctlPolHiCurAcpModeEncpdENRSVDautoModeEnzRSVD
R-0RW-0RW-XR/RW-0R/RW-0RW-0RW-XR-0
Table 8-11 Device Configuration Register 2 Field Descriptions
BitFieldTypeResetDescription
7RSVDR0

Reserved

Read only, returns 0 when read.

6customBCfeaturesRW0

Custom battery charging feature enable

This bit controls the ability to write to the battery charging feature configuration controls.

0 = The HiCurAcpModeEn and cpdEN bits are read only and the values are loaded from the OTP ROM.

1 = The HiCurAcpModeEn and cpdEN, bits are R/W and can be loaded by EEPROM or written by SMBus from this register.

This bit can be written simultaneously with HiCurAcpModeEn and cpdEN.

5pwrctlPolRWX

Power enable polarity

This bit is loaded at the deassertion of reset with the value of the
PWRCTL_POL pin.

0 = PWRCTL polarity is active low.

1 = PWRCTL polarity is active high.

When the TUSB4041I-Q1 device is in I2C mode, the TUSB4041I-Q1 device loads this bit from the contents of the EEPROM.

When the TUSB4041I-Q1 device is in SMBUS mode, the value can be overwritten by an SMBus host.

4HiCurAcpModeEnR/RW0

High-current ACP mode enable

This bit enables the high-current tablet charging mode when the automatic battery charging mode is enabled for downstream ports.

0 = High-current divider mode disabled. Legacy current divider mode enabled.

1 = High-current divider mode enabled

This bit is read only unless the customBCfeatures bit is set to 1. If customBCfeatures is 0, the value of this bit reflects the value of the
OTP ROM HiCurAcpModeEn bit.

3cpdENRRW0

Enable device attach detection

This bit enables device attach detection (such as a cell-phone detect) when auto mode is enabled.

0 = Device attach detect is disabled in auto mode.

1 = Device attach detect is enabled in auto mode.

This bit is read only unless the customBCfeatures bit is set to 1. If
customBCfeatures is 0, the value of this bit reflects the value of the OTP ROM cpdEN bit.

2RSVDRW0Reserved
1autoModeEnzRWX

Automatic mode enable(1)

This bit is loaded at the deassertion of reset with the value of the
AUTOENz/HS_SUSPEND pin.

The automatic mode only applies to downstream ports with battery charging enabled when the upstream port is not connected. Under these conditions:

0 = Automatic mode battery charging features are enabled.

1 = Automatic mode is disabled; only battery-charging DCP mode is supported.

0RSVDR0

Reserved

Read only, returns 0 when read.

(1) When the upstream port is connected, battery charging 1.2 CDP mode is supported on all ports that are enabled for battery charging support regardless of the value of this bit, with the exception of port 1. CDP on port 1 is not supported when automatic mode is enabled.