JAJSNA4A May 2024 – September 2024 TUSB521-Q1
PRODUCTION DATA
For further programmability, the TUSB521-Q1 can be controlled using I2C. The SCL and SDA pins are used for I2C clock and I2C data respectively.
A1 PIN LEVEL |
SSEQ0/A0 PIN LEVEL |
BIT 7 (MSB) | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 (W/R) |
---|---|---|---|---|---|---|---|---|---|
0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0/1 |
0 | R | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0/1 |
0 | F | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0/1 |
0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0/1 |
R | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0/1 |
R | R | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0/1 |
R | F | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0/1 |
R | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0/1 |
F | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0/1 |
F | R | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0/1 |
F | F | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0/1 |
F | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0/1 |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0/1 |
1 | R | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0/1 |
1 | F | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0/1 |
1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0/1 |