JAJSNA4A May   2024  – September 2024 TUSB521-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 4-Level Inputs
      3. 7.3.3 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 USB 3.2 2:1 MUX Description
      2. 7.4.2 Linear EQ Configuration
      3. 7.4.3 USB3.2 Modes
      4. 7.4.4 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB521-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB SSTX1/2 Receiver Configuration
        2. 8.2.2.2 USB RX1/2 Receiver Configuration
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 USB3.2 Control/Status Registers (address = 0x20) [reset = 00000000]
    3. 9.3 USB3.2 Control/Status Registers (address = 0x21) [reset = 00000000]
    4. 9.4 USB3.2 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.1 TUSB521-Q1 I2C Target Behavior

TUSB521-Q1 I2C Write with DataFigure 7-2 I2C Write with Data

Use the following procedure to write data to TUSB521-Q1 I2C registers (refer to Figure 7-2):

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB521-Q1 7-bit address and a zero-value W/R bit to indicate a write cycle.
  2. The TUSB521-Q1 acknowledges the address cycle.
  3. The controller presents the register offset within TUSB521-Q1 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB521-Q1 acknowledges the sub-address cycle.
  5. The controller presents the first byte of data to be written to the I2C register.
  6. The TUSB521-Q1 acknowledges the byte transfer.
  7. The controller can continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB521-Q1.
  8. The controller terminates the write operation by generating a stop condition (P).

TUSB521-Q1 I2C Read Without Repeated StartFigure 7-3 I2C Read Without Repeated Start

Use the following procedure to read the TUSB521-Q1 I2C registers without a repeated Start (refer Figure 7-3).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB521-Q1 7-bit address and a zero-value W/R bit to indicate a read cycle.
  2. The TUSB521-Q1 acknowledges the 7-bit address cycle.
  3. Following the acknowledge the controller continues sending clock.
  4. The TUSB521-Q1 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB521-Q1 shall start at the register offset specified in the write.
  5. The TUSB521-Q1 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  6. If an ACK is received, the TUSB521-Q1 transmits the next byte of data as long as controller provides the clock. If a NAK is received, the TUSB521-Q1 stops providing data and waits for a stop condition (P).
  7. The controller terminates the write operation by generating a stop condition (P).

TUSB521-Q1 I2C Read with Repeated StartFigure 7-4 I2C Read with Repeated Start

Use the following procedure to read the TUSB521-Q1 I2C registers with a repeated Start (refer Figure 7-4).

  1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB521-Q1 7-bit address and a zero-value W/R bit to indicate a write cycle.
  2. The TUSB521-Q1 acknowledges the 7-bit address cycle.
  3. The controller presents the register offset within TUSB521-Q1 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB521-Q1 acknowledges the register offset cycle.
  5. The controller presents a repeated start condition (Sr).
  6. The controller initiates a read operation by generating a start condition (S), followed by the TUSB521-Q1 7-bit address and a one-value W/R bit to indicate a read cycle.
  7. The TUSB521-Q1 acknowledges the 7-bit address cycle.
  8. The TUSB521-Q1 transmit the contents of the memory registers MSB-first starting at the register offset.
  9. The TUSB521-Q1 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  10. If an ACK is received, the TUSB521-Q1 transmits the next byte of data as long as controller provides the clock. If a NAK is received, the TUSB521-Q1 stops providing data and waits for a stop condition (P).
  11. The controller terminates the read operation by generating a stop condition (P).

TUSB521-Q1 I2C Write Without DataFigure 7-5 I2C Write Without Data

Use the following procedure to set a starting sub-address for I2C reads (refer to Figure 7-5).

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB521-Q1 7-bit address and a zero-value W/R bit to indicate a write cycle.
  2. The TUSB521-Q1 acknowledges the address cycle.
  3. The controller presents the register offset within TUSB521-Q1 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB521-Q1 acknowledges the register offset cycle.
  5. The controller terminates the write operation by generating a stop condition (P).

Note:

After initial power up, if no register offset is included for the read procedure (refer to Figure 7-3), then reads start at register offset 00h and continue byte by byte through the registers until the I2C controller terminates the read operation. During a read operation, the TUSB521-Q1 auto-increments the I2C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C controller.

Software must only access (read or write) addresses detailed in this document. Accessing reserved or undocumented addresses can result in TUSB521-Q1 entering an undefined state.