JAJSE19G October 2017 – November 2022 TUSB564
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DP0EQ_SEL | DP2EQ_SEL | ||||||
R/W/U | R/W/U |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | DP0EQ_SEL | R/W/U | 0000 | Field selects EQ level for DP lane 0. When EQ_OVERRIDE = 1’b0, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change the EQ setting for DP lane 0 based on value written to this field. |
3:0 | DP2EQ_SEL | R/W/U | 0000 | Field selects EQ level for DP lane 2. When EQ_OVERRIDE = 1’b0, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change the EQ setting for DP lane 2 based on value written to this field. |