JAJSE19 データシート

JAJSE19G October 2017 – November 2022 TUSB564

PRODUCTION DATA

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

Figure 8-1 Power-Up Timing

Table 8-8 Power-Up Timing⁽¹⁾⁽²⁾

PARAMETER		MIN	MAX	UNIT
t_{d_pg}	V_CC (minimum) to Internal Power Good asserted high		500	µs
t_{cfg_su}	CFG(1) pins setup(2)	50		µs
t_{cfg_hd}	CFG(1) pins hold	10		µs
t_{CTL_DB}	CTL[1:0] and FLIP pin debounce		16	ms
t_{VCC_RAMP}	VCC supply ramp requirement	0.1	100	ms

(1) Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0].

(2) Recommend CFG pins are stable when V_CC is at minimum value.