SLLSEE6B July   2014  – January 2016 TUSB8041-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics, 3.3-V I/O
    6. 7.6 Timing Requirements, Power-Up
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Registers
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8041-Q1 Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8041-Q1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PAP|64
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PAP Package
64 Pin
(Top View)
TUSB8041-Q1 po_pap_llsee6.gif Figure 1. TUSB8041-Q1 Pin Diagram

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
Clock and Reset Signals
GRSTz 18 I
PU		 Global power reset. This reset brings all of the TUSB8041-Q1 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.
XI 30 I Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
XO 29 O Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
USB Upstream Signals
USB_SSTXP_UP 23 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP 24 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP 26 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_UP 27 I USB SuperSpeed receiver differential pair (negative)
USB_DP_UP 21 I/O USB High-speed differential transceiver (positive)
USB_DM_UP 22 I/O USB High-speed differential transceiver (negative)
USB_R1 32 I Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.
USB_VBUS 16 I USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground through a 10-kΩ ±1% resistor from the signal to ground.
USB Downstream Signals
USB_SSTXP_DN1 35 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN1 36 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN1 38 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN1 39 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN1 33 I/O USB High-speed differential transceiver (positive)
USB_DM_DN1 34 I/O USB High-speed differential transceiver (negative)
PWRCTL1/BATEN1 4 I/O, PD USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 1.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR1z 14 I, PU USB Port 1 Over-Current Detection. This pin is used to connect the over current output of the downstream port power switch for Port 1.
0 = An over current event has occurred
1 = An over current event has not occurred
This pin can be left unconnected if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power switch.
USB_SSTXP_DN2 43 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN2 44 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN2 46 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN2 47 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN2 41 I/O USB High-speed differential transceiver (positive)
USB_DM_DN2 42 I/O USB High-speed differential transceiver (negative)
PWRCTL2/BATEN2 3 I/O, PD USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 2.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 2 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR2z 15 I, PU USB Port 2 Over-Current Detection. This pin is used to connect the over current output of the downstream port power switch for Port 2.
0 = An over current event has occurred
1 = An over current event has not occurred
This pin be left unconnected if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power switch.
USB_SSTXP_DN3 51 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN3 52 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN3 54 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN3 55 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN3 49 I/O USB High-speed differential transceiver (positive)
USB_DM_DN3 50 I/O USB High-speed differential transceiver (negative)
PWRCTL3/BATEN3 1 I/O, PD USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 3.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 3 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR3z 12 I, PU USB Port 3 Over-Current Detection. This pin is used to connect the over current output of the downstream port power switch for Port 3.
0 = An over current event has occurred
1 = An over current event has not occurred
This pin can be left unconnected if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power switch.
USB_SSTXP_DN4 58 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN4 59 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN4 61 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN4 62 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN4 56 I/O USB High-speed differential transceiver (positive)
USB_DM_DN4 57 I/O USB High-speed differential transceiver (negative)
PWRCTL4/BATEN4 64 I/O, PD USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 4.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 4 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR4z 11 I, PU USB Port 4 Over-Current Detection. This pin is used to connect the over current output of the downstream port power switch for Port 4.
0 = An over current event has occurred
1 = An over current event has not occurred
This pin can be left unconnected if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power switch.
I2C/SMBUS Signals
SCL/SMBCLK 6 I/O, PD I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
Can be left unconnected if external interface not implemented.
SDA/SMBDAT 5 I/O, PD I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
Can be left unconnected if external interface not implemented.
SMBUSz/SS_SUSPEND 7 I/O, PU I2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled at the de-assertion of reset set I2C or SMBus mode as follows:
1 = I2C Mode Selected
0 = SMBus Mode Selected
Can be left unconnected if external interface not implemented.
After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if enabled through the Additional Feature Configuration register. When enabled a value of 1 indicates the connection is suspended.
Test and Miscellaneous Signals
FULLPWRMGMTz/
SMBA1/SS_UP		 8 I/O, PD Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status Upstream port.
The value of the pin is sampled at the de-assertion of reset to set the power switch control follows:
0 = Power switching and over current inputs supported
1 = Power switching and over current inputs not supported
Full power management is the ability to control power to the downstream ports of the TUSB8041-Q1 using PWRCTL[4:1]/BATEN[4:1].
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave address bit 1.
Can be left unconnected if full power management and SMBus are not implemented.
After reset, this signal indicates the SuperSpeed USB connection status of the upstream port if enabled through the Additional Feature Configuration register. When enabled a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable port.
Note: Power switching must be supported for battery charging applications.
PWRCTL_POL 9 I/O, PU Power Control Polarity.
The value of the pin is sampled at the de-assertion of reset to set the polarity of PWRCTL[4:1].
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
GANGED/SMBA2/
HS_UP		 10 I/O, PD Ganged operation enable/SMBus Address bit 2/HS Connection Status Upstream Port.
The value of the pin is sampled at the de-assertion of reset to set the power switch and over current detection mode as follows:
0 = Individual power control supported when power switching is enabled
1 = Power control gangs supported when power switching is enabled
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave address bit 2.
After reset, this signal indicates the High-speed USB connection status of the upstream port if enabled through the Additional Feature Configuration register. When enabled a value of 1 indicates the upstream port is connected to a High-speed USB capable port.
Note: Individual power control must be enabled for battery charging applications.
AUTOENz/
HS_SUSPEND		 13 I/O, PU Automatic Charge Mode Enable/HS Suspend Status.
The value of the pin is sampled at the de-assertion of reset to determine if automatic mode is enabled as follows:
0 = Automatic Mode is enabled on ports that are enabled for battery charging when the hub is unconnected. Please note that CDP is not supported on Port 1 when operating in Automatic mode.
1 = Automatic Mode is disabled
This value is also used to set the autoEnz bit in the Battery Charging Support Register.
After reset, this signal indicates the High-speed USB Suspend status of the upstream port if enabled through the Additional Feature Configuration register. When enabled a value of 1 indicates the connection is suspended.
TEST 17 I, PD This pin is reserved for factory test.
Power and Ground Signals
VDD 19, 25,
37, 45
53, 60,
63 		PWR 1.1-V power rail
VDD33 2, 20,
31, 48 		PWR 3.3-V power rail
VSS THERMAL PAD PWR Ground. Thermal pad must be connected to ground.
NC 28, 40 — No connect, leave floating