SLLSEE6B July   2014  – January 2016 TUSB8041-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics, 3.3-V I/O
    6. 7.6 Timing Requirements, Power-Up
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Registers
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8041-Q1 Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8041-Q1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage Range VDD Steady-state supply voltage –0.3 1.4 V
VDD33 Steady-state supply voltage –0.3 3.8 V
Voltage Range USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals -0.3 1.4 V
XI terminals -0.3 2.45 V
All other terminals -0.3 3.8 V
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 Classification Level H2(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 Classification Level C4B Corner pins ±750
Other pins ±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD 1.V1 supply voltage 0.99 1.1 1.26 V
VDD33 3.3V supply voltage 3 3.3 3.6 V
USB_VBUS Voltage at USB_VBUS PAD 0 1.155 V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 105 °C

7.4 Thermal Information

THERMAL METRIC(1) TUSB8041-Q1 UNIT
PAP
64 PINS
RθJA Junction-to-ambient thermal resistance(2) 26.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance(3) 11.5
RθJB Junction-to-board thermal resistance(4) 10.4
ψJT Junction-to-top characterization parameter(5) 0.2
ψJB Junction-to-board characterization parameter(6) 10.3
RθJCbot Junction-to-case (bottom) thermal resistance(7) 0.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer

7.5 Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)
PARAMETER OPERATION TEST CONDITIONS MIN MAX UNIT
VIH High-level input voltage(1) VDD33 2 VDD33 V
VIL Low-level input voltage(1) VDD33 0 0.8 V
JTAG pins only 0 0.55
VI Input voltage 0 VDD33 V
VO Output voltage(2) 0 VDD33 V
tt Input transition time (trise and tfall) 0 25 ns
Vhys Input hysteresis(3) 0.13 x VDD33 V
VOH High-level output voltage VDD33 IOH = -4 mA 2.4 V
VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V
IOZ High-impedance, output current(2) VDD33 VI = 0 to VDD33 ±20 µA
IOZP High-impedance, output current with internal pullup or pulldown resistor(4) VDD33 VI = 0 to VDD33 ±250 µA
II Input current(5) VDD33 VI = 0 to VDD33 ±15 µA
(1) Applies to external inputs and bidirectional buffers.
(2) Applies to external outputs and bidirectional buffers.
(3) Applies to GRSTz.
(4) Applies to pins with internal pullups/pulldowns.
(5) Applies to external input buffers.

7.6 Timing Requirements, Power-Up

PARAMETER DESCRIPTION MIN TYP MAX UNIT
td1 VDD33 stable before VDD stable(3) See (2) ms
td2 VDD and VDD33 stable before de-assertion of GRSTz 3 ms
tsu_io Setup for MISC inputs(1) sampled at the de-assertion of GRSTz 0.1 µs
thd_io Hold for MISC inputs(1) sampled at the de-assertion of GRSTz 0.1 µs
tVDD33_RAMP VDD33 supply ramp requirements 0.2 100 ms
tVDD_RAMP VDD supply ramp requirements 0.2 100 ms
(1) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.
(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.
(3) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.
TUSB8041-Q1 pwr_up_timing_sllsee4.gif Figure 2. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at TA = 25°C
PARAMETER VDD33 VDD UNIT
3.3 V 1.1 V
LOW POWER MODES
Power On (after Reset)                    2.3 28 mA
Upstream Disconnect 2.3 28 mA
Suspend                                   2.5 33 mA
ACTIVE MODES (US state / DS State)
3.0 host / 1 SS Device and Hub in U1 / U2 49 225 mA
3.0 host / 1 SS Device and Hub in U0 49 366 mA
3.0 host / 2 SS Devices and Hub in U1 / U2 49 305 mA
3.0 host / 2 SS Devices and Hub in U0 49 508 mA
3.0 host / 3 SS Devices and Hub in U1 / U2 49 380 mA
3.0 host / 3 SS Devices and Hub in U0 49 661 mA
3.0 host / 4 SS Devices and Hub in U1 / U2 49 455 mA
3.0 host / 4 SS Devices and Hub in U0 49 778 mA
3.0 host / 1 SS Device in U0 and 1 HS Device 85 395 mA
3.0 host / 2 SS Devices in U0 and 2 HS Devices 99 554 mA
2.0 host / HS Device 45 63 mA
2.0 host / 4 HS Devices 76 86 mA