JAJSHM8 June   2019 TUSB8042A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
        1. Table 6. Bit Descriptions – ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
        1. Table 7. Bit Descriptions – Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
        1. Table 8. Bit Descriptions – Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
        1. Table 9. Bit Descriptions – Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
        1. Table 10. Bit Descriptions – Product ID MSB Register
      7. 8.5.7  Device Configuration Register
        1. Table 11. Bit Descriptions – Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
        1. Table 12. Bit Descriptions – Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
        1. Table 13. Bit Descriptions – Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
        1. Table 14. Bit Descriptions – Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
        1. Table 15. Bit Descriptions – Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
        1. Table 16. Bit Descriptions – USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
        1. Table 17. Bit Descriptions – UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
        1. Table 18. Bit Descriptions – Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
        1. Table 19. Bit Descriptions – Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
        1. Table 20. Bit Descriptions – Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
        1. Table 21. Bit Descriptions – Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
        1. Table 22. Bit Descriptions – Product String Length Register
      19. 8.5.19 Device Configuration Register 3
        1. Table 23. Bit Descriptions – Device Configuration Register 3
      20. 8.5.20 USB 2.0 Only Port Register
        1. Table 24. Bit Descriptions – USB 2.0 Only Port Register
      21. 8.5.21 Serial Number String Registers
        1. Table 25. Bit Descriptions – Serial Number Registers
      22. 8.5.22 Manufacturer String Registers
        1. Table 26. Bit Descriptions – Manufacturer String Registers
      23. 8.5.23 Product String Registers
        1. Table 27. Bit Descriptions – Product String Byte N Register
      24. 8.5.24 Additional Feature Configuration Register
        1. Table 28. Bit Descriptions – Additional Feature Configuration Register
      25. 8.5.25 SMBus Device Status and Command Register
        1. Table 29. Bit Descriptions – SMBus Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8042A Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8042A Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low Power Modes
IDD_PWRON VDD current after Power On (after reset) VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C; 18 mA
IDD33_PWRON VDD33 current after Power On (after reset) VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C; 2 mA
IDD_UPDISC VDD current when upstream port is disconnected VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C; 21 mA
IDD33_UPDISC VDD33 current when upstream port is disconnected VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C; 2 mA
IDD_SUSPEND VDD current in Suspend VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C; 20 mA
IDD33_SUSPEND VDD33 current in Suspend VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C; 2 mA
Active Power Modes (US State / DS State)
IDD_SMBUS VDD current during SMbus programming. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   275   mA
IDD33_SMBUS VDD33 current during SMbus programming VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   75   mA
IDD_3H_1SS_0HS_U12 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 1 SS device, and 0 HS device. Links in U1/U2. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   215   mA
IDD33_3H_1SS_0HS_U12 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 1 SS device, and 0 HS device. Links in U1/U2. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_1SS_0HS_U0 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 1 SS device, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   330   mA
IDD33_3H_1SS_0HS_U0 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 1 SS device, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_2SS_0HS_U12 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 2 SS devices, and 0 HS device. Links in U1/U2 VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   301   mA
IDD33_3H_2SS_0HS_U12 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 2 SS devices, and 0 HS device. Links in U1/U2 VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_2SS_0HS_U0 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 2 SS devices, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   440   mA
IDD33_3H_2SS_0HS_U0 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 2 SS devices, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_3SS_0HS_U12 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 3 SS devices, and 0 HS device. Links in U1/U2 VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   360   mA
IDD33_3H_3SS_0HS_U12 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 3 SS devices, and 0 HS device. Links in U1/U2 VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_3SS_0HS_U0 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 3 SS devices, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   560   mA
IDD33_3H_3SS_0HS_U0 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 3 SS devices, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_4SS_0HS_U12 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 4 SS devices, and 0 HS device. Links in U1/U2 VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   467   mA
IDD33_3H_4SS_0HS_U12 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 4 SS devices, and 0 HS device. Links in U1/U2 VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_4SS_0HS_U0 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 4 SS devices, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   650   mA
IDD33_3H_4SS_0HS_U0 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 4 SS devices, and 0 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_3H_1SS_1HS_U0 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 1 SS device, and 1 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   372   mA
IDD33_3H_1SS_1HS_U0 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 1 SS devices, and 1 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   84   mA
IDD_3H_1SS_2HS_U0 VDD current upstream port connected to USB 3.0 Host, downstream port(s) connected to 2 SS device, and 2 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   480   mA
IDD33_3H_1SS_2HS_U0 VDD33 current upstream port connected to USB 3.0 Host, downstream port(s) connected to 2 SS devices, and 2 HS device. Links in U0. VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   95   mA
IDD_2H_0SS_1HS VDD current upstream port connected to USB 2.0 Host, downstream port(s) connected to 0 SS device, and 1 HS device.  VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD33_2H_0SS_1HS VDD33 current upstream port connected to USB 2.0 Host, downstream port(s) connected to 0 SS devices, and 1 HS device.  VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   45   mA
IDD_2H_0SS_4HS VDD current upstream port connected to USB 2.0 Host, downstream port(s) connected to 0 SS device, and 4 HS device.  VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   74   mA
IDD33_2H_0SS_4HS VDD33 current upstream port connected to USB 2.0 Host, downstream port(s) connected to 0 SS devices, and 4 HS device.  VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;   76   mA
3.3V I/O
VIH High-level input voltage(1) 2 3.6 V
VIL Low-level input voltage(1) 0 0.8 V
VI Input voltage 0 3.6 V
VO Output voltage(2) 0 3.6 V
tt Input transition time (tRISE and tFALL) 25 ns
VHYS Input hysteresis(3) 1.3 x VDD33 V
VOH High-level output voltage IOH = -4 mA 2.4 V
VOL Low-level output voltage IOH = 4 mA 0.4 V
IOZP High-impedance output current with internal pullup or pulldown resistor.(4) VI = 0 to VDD33; -250 250 µA
II Input current(5) VI = 0 to VDD33; -15 15 µA
RPD Internal pull-down resistance 13.5 19 27.5 kΩ
RPU Internal pull-up resistance 14.5 19 25 kΩ
(1) Applies to external inputs and bi-directional buffers
(2) Applies to external outputs and bi-directional buffers
(3) Applies to GRSTZ
(4) Applies to pins with internal pullups/pulldowns.
(5) Applies to external input buffers