JAJSHM9 June   2019 TUSB8043A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 I2C Programming Support Using Internal HID to I2C Interface
        1. 8.3.3.1 SET REPORT (Output)
        2. 8.3.3.2 GET REPORT (Feature)
        3. 8.3.3.3 GET REPORT (Input)
      4. 8.3.4 One Time Programmable (OTP) Configuration
      5. 8.3.5 Clock Generation
      6. 8.3.6 Crystal Requirements
      7. 8.3.7 Input Clock Requirements
      8. 8.3.8 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
        1. Table 7. Bit Descriptions – ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
        1. Table 8. Bit Descriptions – Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
        1. Table 9. Bit Descriptions – Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
        1. Table 10. Bit Descriptions – Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
        1. Table 11. Bit Descriptions – Product ID MSB Register
      7. 8.5.7  Device Configuration Register
        1. Table 12. Bit Descriptions – Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
        1. Table 13. Bit Descriptions – Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
        1. Table 14. Bit Descriptions – Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
        1. Table 15. Bit Descriptions – Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
        1. Table 16. Bit Descriptions – Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
        1. Table 17. Bit Descriptions – USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
        1. Table 18. Bit Descriptions – UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
        1. Table 19. Bit Descriptions – Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
        1. Table 20. Bit Descriptions – Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
        1. Table 21. Bit Descriptions – Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
        1. Table 22. Bit Descriptions – Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
        1. Table 23. Bit Descriptions – Product String Length Register
      19. 8.5.19 Device Configuration Register 3
        1. Table 24. Bit Descriptions – Device Configuration Register 3
      20. 8.5.20 USB 2.0 Only Port Register
        1. Table 25. Bit Descriptions – USB 2.0 Only Port Register
      21. 8.5.21 Serial Number String Registers
        1. Table 26. Bit Descriptions – Serial Number Registers
      22. 8.5.22 Manufacturer String Registers
        1. Table 27. Bit Descriptions – Manufacturer String Registers
      23. 8.5.23 Product String Registers
        1. Table 28. Bit Descriptions – Product String Byte N Register
      24. 8.5.24 Additional Feature Configuration Register
        1. Table 29. Bit Descriptions – Additional Feature Configuration Register
      25. 8.5.25 SMBus Device Status and Command Register
        1. Table 30. Bit Descriptions – SMBus Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8043A Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8043A Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 I2C EEPROM Operation

The TUSB8043A supports a single-master, standard mode (100 KHz) or fast mode (400KHz) connection to a dedicated I2C EEPROM when the I2C interface mode is enabled. In I2C mode, the TUSB8043A reads the contents of the EEPROM at bus address 1010000b using 7-bit addressing starting at address 0. The TUSB8043A reads the entire EEPROM contents using a single burst read transaction. The burst read transaction ends when the address reaches FFh.

If the value of the EEPROM contents at address byte 00h equals 55h, the TUSB8043A loads the configuration registers according to the EEPROM map. If the first byte is not 55h, the TUSB8043A exits the I2C mode and continues execution with the default values in the configuration registers. The hub is not connect on the upstream port until the configuration is completed.

NOTE

The bytes located above offset Ah are optional. The requirement for data in those addresses is dependent on the options configured in the Device Configuration, and Device Configuration 2 registers.

The minimum size I2C EEPROM required is 2Kbit.

For details on I2C operation refer to the UM10204 I2C-bus Specification and User Manual.