JAJSMI5A November   2021  – March 2022 TXU0102

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions—TXU0102
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    7. 7.7  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    8. 7.8  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    9. 7.9  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    10. 7.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    11. 7.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    12. 7.12 Operating Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Load Circuit and Voltage Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 9.3.1.1 Inputs with Integrated Static Pull-Down Resistors
      2. 9.3.2 Control Logic (OE) with VCC(MIN) Circuitry
      3. 9.3.3 Balanced High-Drive CMOS Push-Pull Outputs
      4. 9.3.4 VCC Isolation and VCC Disconnect
      5. 9.3.5 Over-Voltage Tolerant Inputs
      6. 9.3.6 Glitch-Free Power Supply Sequencing
      7. 9.3.7 Negative Clamping Diodes
      8. 9.3.8 Fully Configurable Dual-Rail Design
      9. 9.3.9 Supports High-Speed Translation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Regulatory Requirements
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCU|8
  • DTM|8
  • DTT|8
サーマルパッド・メカニカル・データ
発注情報

9.1 Overview

The TXU0102 is a 4-bit translating transceiver that uses two individually configurable power-supply rails. The device is operational with VCCA and VCCB supplies as low as 1.1 V and as high as 5.5 V. Additionally, the device can be operated with VCCA = VCCB. The A port is designed to track VCCA, and the B port is designed to track VCCB.

The TXU0102 device is designed for asynchronous communication between data buses, and transmits data with fixed direction from the A bus to the B bus on some channels and from the B bus to the A bus on the remaining channels. The output-enable input (OE) is used to disable the outputs so the buses are effectively isolated. The output-enable pin of the TXU0102 (OE) can be referenced to either VCCA or VCCB. The OE pin can be left floating or externally pulled down to ground to ensure the high-impedance state of the level shifter outputs during power up or power down.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or sourced into an input or output while the device is powered down.

The VCC isolation or VCC disconnect feature ensures that if either VCC is less than 100 mV or disconnected with the complementary supply within recommended operating conditions, outputs are disabled and set to the high-impedance state while the supply current is maintained. The Ioff-float circuitry ensures that no excessive current is drawn from or sourced into an input or output while the supply is floating.

Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.