JAJSK71X january   1976  – june 2023 UA78L

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: UA78L02 (Legacy Chip Only)
    6. 6.6  Electrical Characteristics: UA78L033 (New Chip Only)
    7. 6.7  Electrical Characteristics: UA78L05 (Both Legacy and New Chip)
    8. 6.8  Electrical Characteristics: UA78L12 (Both Legacy and New Chip)
    9. 6.9  Electrical Characteristics: UA78L06 (Legacy Chip Only)
    10. 6.10 Electrical Characteristics: UA78L08 (Legacy Chip Only)
    11. 6.11 Electrical Characteristics: UA78L09 (Legacy Chip Only)
    12. 6.12 Electrical Characteristics: UA78L10 (Legacy Chip Only)
    13. 6.13 Electrical Characteristics: UA78L15 (Both Legacy and New Chip)
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Thermal Shutdown
      3. 7.3.3 Dropout Voltage (VDO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Power Dissipation (PD)
        3. 8.2.2.3 Estimating Junction Temperature
        4. 8.2.2.4 External Capacitor Requirements
        5. 8.2.2.5 Overload Recovery
        6. 8.2.2.6 Reverse Current
        7. 8.2.2.7 Polarity Reversal Protection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Positive Regulator in Negative Configuration
      2. 8.3.2 Current Limiter Circuit
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • PK|3
  • LP|3
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics: UA78L05 (Both Legacy and New Chip)

at specified junction temperature, VI = 10 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT
Output voltage VI = 7 V to 20 V, and
IO = 1 mA to 40 mA (for legacy chip)		 TJ = 25°C UA78L05C 4.6 5 5.4 V
UA78L05AC and UA78L05AI 4.8 5 5.2
TJ = full range UA78L05C 4.5 5.5
UA78L05AC and UA78L05AI 4.75 5.25
IO = 1 mA to 70 mA, and
TJ = full range (for legacy chip)		 UA78L05C 4.5 5.5
UA78L05AC and UA78L05AI 4.75 5.25
VI = 7 V to 20 V, and
IO = 1 mA to 40 mA (for new chip)		 TJ = 25°C UA78L05C 4.95 5 5.15
UA78L05AC and UA78L05AI 4.95 5 5.15
TJ = full range UA78L05C 4.85 5.15
UA78L05AC and UA78L05AI 4.85 5.15
IO = 1 mA to 70 mA, and
TJ = full range (for new chip)		 UA78L05C 4.80 5.14
UA78L05AC and UA78L05AI 4.80 5.14
Input voltage regulation VI = 7 V to 20 V, and
TJ = 25°C (for legacy chip)		 UA78L05C 32 200 mV
UA78L05AC and UA78L05AI 32 150
VI = 8 V to 20 V, and
TJ = 25°C (for legacy chip)		 UA78L05C 26 150
UA78L05AC and UA78L05AI 26 100
VI = 7 V to 20 V, and
TJ = 25°C (for new chip)		 UA78L05C 32 33
UA78L05AC and UA78L05AI 32 33
VI = 8 V to 20 V, and
TJ = 25°C (for new chip)		 UA78L05C 26 28
UA78L05AC and UA78L05AI 26 28
Ripple rejection VI = 8 V to 18 V, f = 120 Hz,
and TJ = 25°C (for legacy chip)		 UA78L05C 40 49 dB
UA78L05AC and UA78L05AI 41 49
VI = 8 V to 18 V, f = 120 Hz,
and TJ = 25°C (for new chip)		 UA78L05C 48 55
UA78L05AC and UA78L05AI 48 55
Output voltage regulation for legacy chip IO = 1 mA to 100 mA, and TJ = 25°C 15 60 mV
IO = 1 mA to 40 mA, and TJ = 25°C 8 30
for new chip IO = 1 mA to 100 mA, and TJ = 25°C 15 35
IO = 1 mA to 40 mA, and TJ = 25°C 8 15
Output noise voltage for legacy chip f = 10 Hz to 100 kHz, and TJ = 25°C 42 μV
for new chip f = 10 Hz to 100 kHz, and TJ = 25°C 125
Dropout voltage for legacy chip TJ = 25°C 1.7 V
for new chip 1.7 V
Bias current for legacy chip TJ = 25°C 3.8 6 mA
TJ = 125°C 5.5 mA
for new chip TJ = 25°C 3.53 3.95 mA
TJ = 125°C 4.0
Bias current change VI = 8 V to 20 V, and TJ = full range (for new legacy chip) 1.5 mA
IO = 1 mA to 40 mA, and
TJ = full range (for legacy chip)		 UA78L05C 1.5 mA
UA78L05AC and UA78L05AI 1.5 mA
VI = 8 V to 20 V, and TJ = full range (for new chip) 0.485 mA
IO = 1 mA to 40 mA, and
TJ = full range (for new chip)		 UA78L05C 0.01
UA78L05AC and UA78L05AI 0.01
(1) Applies to UA78L05C, UA78L05AC and UA78L05AI.
(2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L05C, UA78L05AC is TJ = 0°C to 125°C, and for the UA78L05AI is TJ = –40°C to 125°C. For new chip, temperature range for the UA78L05C, UA78L05AC and UA78L05AI is TJ = –40°C to 125°C.