JAJSSP7U
June 1976 – May 2024
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics: UA78M33 (Both Legacy and New Chip)
5.6
Electrical Characteristics: UA78M05 (Both Legacy and New Chip)
5.7
Electrical Characteristics: UA78M06C (Legacy Chip Only)
5.8
Electrical Characteristics: UA78M08C (Legacy Chip Only)
5.9
Electrical Characteristics: UA78M09 (Legacy Chip Only)
5.10
Electrical Characteristics: UA78M10 (Legacy Chip Only)
5.11
Electrical Characteristics: UA78M12 (Legacy Chip Only)
5.12
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Current Limit
6.3.2
Dropout Voltage (VDO)
6.3.3
Thermal Shutdown
6.4
Device Functional Modes
6.4.1
Normal Operation
6.4.2
Dropout Operation
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Input and Output Capacitor Requirements
7.2.2.2
Power Dissipation (PD)
7.2.2.3
Estimating Junction Temperature
7.2.2.4
External Capacitor Requirements
7.2.2.5
Overload Recovery
7.2.2.6
Reverse Current
7.2.2.7
Polarity Reversal Protection
7.2.3
Application Curves
7.3
System Examples
7.3.1
Positive Regulator in Negative Configuration
7.3.2
Current Limiter Circuit
7.4
Power Supply Recommendations
7.5
Layout
7.5.1
Layout Guidelines
7.5.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Evaluation Module
8.1.2
Device Nomenclature
8.2
ドキュメントの更新通知を受け取る方法
8.3
サポート・リソース
8.4
Trademarks
8.5
静電気放電に関する注意事項
8.6
用語集
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
KVU|3
DCY|4
KCS|3
サーマルパッド・メカニカル・データ
KVU|3
QFND404A
DCY|4
QFND222B
発注情報
jajssp7u_oa
jajssp7u_pm
8.1
Device Support