The UC1825A-SP PWM controller is a radiation hardened version of the standard UC1825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead time control. Frequency accuracy is improved to 6%. Start-up supply current, typically
100 μA, is ideal for offline applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the start-up current specification. In addition each output is capable of
2-A peak currents during transitions.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UC1825A-SP | CDIP (16) | 19.56 mm × 6.92 mm |
UC1825A-SP RHA | CDIP (16) | 19.56 mm × 6.92 mm |
CFP (16) | 10.16 mm × 7.10 mm |
Changes from B Revision (October 2015) to C Revision
Changes from A Revision (January 2009) to B Revision
Functional improvements have also been implemented in this device family. The UC1825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC1825 CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC1825A-SP has dual alternating outputs and the same pin configuration of the UC1825. The UC1825A-SP version parts have UVLO thresholds identical to the original UC1825.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLK/LEB | 4 | O | Output of the internal oscillator. |
CT | 6 | I | Timing capacitor connection pin for oscillator frequency programming. The timing capacitor must be connected to the device ground using minimal trace length. |
EAOUT | 3 | O | Output of the error amplifier for compensation. |
GND | 10 | — | Analog ground return pin. |
ILIM | 9 | I | Input to the current limit comparator. |
INV | 1 | I | Inverting input to the error amplifier. |
NI | 2 | I | Noninverting input to the error amplifier. |
OUTA | 11 | O | High current totem pole output A of the on-chip drive stage. |
OUTB | 14 | O | High current totem pole output B of the on-chip drive stage. |
PGND | 12 | — | Ground return pin for the output driver stage. |
RAMP | 7 | I | Noninverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. |
RT | 5 | I | Timing resistor connection pin for oscillator frequency programming. |
SS | 8 | I | Soft-start input pin that also doubles as the maximum duty cycle clamp. |
VC | 13 | — | Power supply pin for the output stage. This pin must be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths. |
VCC | 15 | — | Power supply pin for the device. This pin must be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths. |
VREF | 16 | O | 5.1-V reference. For stability, the reference must be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. |