SLUS873C January   2009  – December 2016 UC1825A-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Leading Edge Blanking
      2. 8.3.2 UVLO, Soft-Start, and Fault Management
      3. 8.3.3 Active Low Outputs During UVLO
      4. 8.3.4 Control Methods
      5. 8.3.5 Synchronization
      6. 8.3.6 High Current Outputs
      7. 8.3.7 Open Loop Test Circuit
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Auxiliary Supply Voltage
        2. 9.2.2.2  Oscillator Frequency
        3. 9.2.2.3  Preliminary Considerations
        4. 9.2.2.4  Input Power
        5. 9.2.2.5  Primary Current
        6. 9.2.2.6  Sense Resistor R(s)
        7. 9.2.2.7  MOSFET DC Losses
        8. 9.2.2.8  Selection of Core Material
        9. 9.2.2.9  Main Transformer Design
        10. 9.2.2.10 Calculation of Transformer
        11. 9.2.2.11 Minimum Core Size
        12. 9.2.2.12 Core Loss Limited Conditions
        13. 9.2.2.13 Core Geometry Selection
        14. 9.2.2.14 Wire Size Selection
        15. 9.2.2.15 Calculate Secondary RMS Current
        16. 9.2.2.16 Transformer Assembly
        17. 9.2.2.17 Calculation of Winding Resistances and Losses
        18. 9.2.2.18 Transformer Power Losses
        19. 9.2.2.19 Output Section
          1. 9.2.2.19.1 Output Choke Calculations
          2. 9.2.2.19.2 Output Capacitor
          3. 9.2.2.19.3 Output Diodes
        20. 9.2.2.20 UC1825A-SP PWM Control Section
          1. 9.2.2.20.1 Current Limit and Shutdown
          2. 9.2.2.20.2 Ramp
          3. 9.2.2.20.3 Slope Compensation
        21. 9.2.2.21 Closing the Feedback Loop
          1. 9.2.2.21.1 Error Amplifier
          2. 9.2.2.21.2 Control to Output Gain
          3. 9.2.2.21.3 Error Amplifier Compensation
          4. 9.2.2.21.4 Dynamic Performance
          5. 9.2.2.21.5 Short Circuit
          6. 9.2.2.21.6 Circuit Power Losses
        22. 9.2.2.22 Summary
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Feedback Traces
      2. 11.1.2 Input/Output Capacitors
      3. 11.1.3 Compensation Components
      4. 11.1.4 Traces and Ground Planes
      5. 11.1.5 Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Supply voltage VC, VCC 22 V
IO Source or sink current, DC OUTA, OUTB 0.5 A
IO Source or sink current, pulse (0.5 μs) OUTA, OUTB 2.2 A
Analog inputs INV, NI, RAMP –0.3 to 7 V
ILIM, SS –0.3 to 6 V
Power ground PGND ±0.2 V
Outputs OUTA, OUTB PGND – 0.3 to VC + 0.3 V
ICLK Clock output current CLK/LEB –5 mA
IO(EA) Error amplifier output current EAOUT 5 mA
ISS Soft-start sink current SS 20 mA
IOSC Oscillator charging current RT –5 mA
TJ Operating virtual junction temperature –55 150 °C
Lead temperature 1.6 mm (1/16 inch) from cases for 10 seconds 300 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (TA = TJ = –55°C to 125°C), unless otherwise noted
MIN MAX UNIT
VCC Supply voltage 12 20 V
Sink/source output current (continuous or time average) 0 100 mA
Reference load current 0 10 mA

7.4 Thermal Information

THERMAL METRIC(1) UC1825A-SP UNIT
J (CDIP)
16 PINS
RθJA Junction-to-ambient thermal resistance 55.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance N/A °C/W
RθJB Junction-to-board thermal resistance 33.3 °C/W
ψJT Junction-to-top characterization parameter 10.3 °C/W
ψJB Junction-to-board characterization parameter 35.89 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.024 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = –55°C to 125°C, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE, VREF
VO Ouput voltage TJ = 25°C, IO = 1 mA 5.05 5.1 5.15 V
Line regulation 12 V ≤ VCC ≤ 20 V 2 15 mV
Load regulation 1 mA ≤ IO ≤ 10 mA 5 20 mV
Total output variation Line, load, temperature 5.03 5.17 V
Temperature stability(1) T(min) < TA < T(max) 0.2 0.4 mV/°C
Output noise voltage 10 Hz < f < 10 kHz 50 μVRMS
Short circuit current VREF = 0 V 30 60 90 mA
OSCILLATOR
fOSC Initial accuracy(1) TJ = 25°C 375 400 425 kHz
RT = 6.6 kΩ, CT = 220 pF, TA = 25°C 0.9 1 1.1 MHz
Total variation(1) Line, temperature 350 450 kHz
RT = 6.6 kΩ, CT = 220 pF 0.82 1.18 MHz
Voltage stability 12 V < VCC < 20 V 1%
Temperature stability T(min) < TA < T(max) ±5%
High-level output voltage, clock 3.7 4 V
Low-level output voltage, clock 0 0.2 V
Ramp peak 2.6 2.8 3 V
Ramp valley 0.7 1 1.25 V
Ramp valley-to-peak 1.55 1.8 2 V
IOSC Oscillator discharge current RT = OPEN, VCT = 2 V 8.5 10 11 mA
ERROR AMPLIFIER
Input offset voltage 2 10 mV
Input bias current 0.6 3 μA
Input offset current 0.1 1 μA
Open loop gain 1 V < VO < 4 V 60 95 dB
CMRR Common mode rejection ratio 1.5 V < VCM < 5.5 V 75 95 dB
PSRR Power supply rejection ratio 12 V < VCC < 20 V 85 110 dB
IO(sink) Output sink current VEAOUT = 1 V 1 2.5 mA
IO(src) Output source current VEAOUT = 4 V –0.5 –1.3 mA
High-level output voltage IEAOUT = –0.5 mA 4.5 4.7 5 V
Low-level output voltage IEAOUT = –1 mA 0 0.5 1 V
Gain bandwidth product(1) f = 200 kHz 6 12 MHz
Slew rate(1) 5 7 V/μs
PWM COMPARATOR
IBIAS Bias current, RAMP VRAMP = 0 V –1 –8 μA
Minimum duty cycle 0%
Maximum duty cycle 85%
tLEB Leading edge blanking time RLEB = 2 kΩ, CLEB = 470 pF 300 375 450 ns
RLEB Leading edge blanking resistance VCLK/LEB = 3 V 8.5 10 11.5 kΩ
VZDC Zero DC threshold voltage, EAOUT VRAMP = 0 V 1.10 1.25 1.4 V
tDELAY Delay-to-output time(1) VEAOUT = 5-V to 0-V step 50 120 ns
CURRENT LIMIT, START SEQUENCE, FAULT
ISS Soft-start charge current VSS = 2.5 V 8 14 20 μA
VSS Full soft-start threshold voltage 4.3 5 V
IDSCH Restart discharge current VSS = 2.5 V 100 250 350 μA
ISS Restart threshold voltage 0 V ≤ VILIM ≤ 1.5 V 0.3 0.5 V
IBIAS ILIM bias current 15 μA
ICL Current limit threshold voltage 0.95 1 1.05 V
Overcurrent threshold voltage 1.14 1.2 1.26 V
td Delay-to-output time, ILIM(1) VILIM = 0-V to 2-V step 50 80 ns
OUTPUT
Low-level output saturation voltage IOUT = 20 mA 0.25 0.45 V
IOUT = 200 mA 1.2 2.2
High-level output saturation voltage IOUT = –20 mA 1.9 2.9 V
IOUT = –200 mA 2 3
tr, tf Rise/fall time(1) CL = 1 nF 20 45 ns
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage 8.3 9.2 9.6 V
UVLO hysteresis 0.4 0.8 1.25 V
SUPPLY CURRENT
Isu Start-up current VC = VCC = 8 V 100 300 μA
ICC Input current 28 36 mA
(1) Parameters ensured by design and/or characterization, if not production tested.

7.6 Typical Characteristics

UC1825A-SP graph_11_slus873.gif
Figure 1. Gain: Light Load
UC1825A-SP graph_12_slus873.gif
Figure 2. Gain: Full Load