JAJSGZ7A May   2015  – February 2019 UC1845A-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      VREF放射線ドリフト曲線
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 UVLO
      2. 9.3.2 Reference
      3. 9.3.3 Totem-Pole Output
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Oscillator
        2. 10.2.2.2 Current Sensing and Limiting
        3. 10.2.2.3 Error Amplifier
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Feedback Traces
      2. 12.1.2 Input/Output Capacitors
      3. 12.1.3 Compensation Components
      4. 12.1.4 Traces and Ground Planes
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2.1 Oscillator

The UC1845A-SP oscillator is programmed as shown in Figure 13. Timing capacitor CT is charged from VREF (5 V) through the timing resistor RT, and discharged by an internal current source. The first step in selecting the oscillator components is to determine the required circuit dead time. Once obtained, Figure 14 is used to pinpoint the nearest standard value of CT for a given dead time. Next, the appropriate RT value is interpolated using the parameters for CT and oscillator frequency. Figure 15 shows the RT/CT combinations versus oscillator frequency. The timing resistor can be calculated from the following formula.

Equation 1. UC1845A-SP eqn1_slusci6.gif
UC1845A-SP sch_EA_comp_LUSC14.gifFigure 12. E/A Compensation Circuit for Continuous Boost and Flyback Topologies

The UC1845A-SP has an internal divide-by-two flip-flop driven by the oscillator for a 50% maximum duty cycle. Therefore, their oscillators must be set to run at twice the desired power supply switching frequency.

UC1845A-SP oscillator_LUSC14.gifFigure 13. Oscillator Programming
UC1845A-SP gr_dt_vs_Ct_lusc14.gifFigure 14. Dead Time vs CT (RT > 5 kΩ)
UC1845A-SP gr_RT_freq_lusc14.gifFigure 15. Timing Resistance vs Frequency