SLUS352C January   1997  – December 2015 UC1846 , UC2846 , UC3846 , UC3847

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Sense Amplifier
      2. 7.3.2 Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Current Limit
      2. 7.4.2 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Switching Frequency
        2. 8.2.2.2 Error Amplifier Output Configuration
        3. 8.2.2.3 Parallel Operation Configuration
        4. 8.2.2.4 Design Pulse by Pulse Current Limit Threshold
        5. 8.2.2.5 Soft-Start and Shutdown, Restart Function Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • J|16
  • FK|20
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

J or N, DW Packages
16-Pin CDIP or PDIP, SOIC
Top View
UC1846 UC1847 UC2846 UC2847 UC3846 UC3847 soic16_po.gif
FN or FK Packages
20-Pin PLCC or LCCC
Top View
UC1846 UC1847 UC2846 UC2847 UC3846 UC3847 lcc20_po.gif

Pin Functions

PIN I/O DESCRIPTION
DIL, SOIC NO. PLCC, LCC NO. NAME
1 2 C/S SS I Current limit/soft-start programming
2 3 VREF O 5.1-V reference voltage output
3 4 C/S – I Current sense comparator inverting input
4 5 C/S + I Current sense comparator non-inverting input
5 7 E/A + I Error amplifier inverting input
6 8 E/A – I Error amplifier inverting input
7 9 COMP I/O Error amplifier output and input to the PWM comparator
8 10 CT I Oscillator frequency programming capacitor pin
9 12 CR I Oscillator frequency programming resistor pin
10 13 Sync I/O Synchronization out from master controller or input of slave controller
11 14 A Out O PWM drive signal output A, Pin11 and P14 are complementary
12 15 GND G All signals are referenced to this node
13 17 VC I Bias supply input for output stage
14 18 B Out O PWM drive signal output B, Pin11 and P14 are complementary
15 19 VIN I Bias supply input
16 20 Shutdown I External shutdown signal input
— 1, 6, 11, 16 N/C