Table 1. Design Parameters

Table 2. Output Duty Cycle

Table 3. Additional Controls of the Output Duty Cycle

9.2.2.1 Protection Inputs

ENA (Enable): The ENA input must reach 2.5 V before the VREF and GTDRV outputs are enabled. This provides a means to shut down the gate in case of trouble, or to add a time delay at power up. A hysteresis gap of 200 mV is provided at this terminal to prevent erratic operation. Undervoltage protection is provided directly at VCC, where the on and off thresholds are 16 V and 10 V. If the ENA input is unused, it must be pulled up to V_CC through a current-limiting resistor of 100 kΩ.

SS (Soft Start): The voltage at SS pin reduces the reference voltage used by the error amplifier to regulate the output DC voltage. With SS open, the reference voltage is typically 7.5 V. An internal current source delivers approximately 14 mA from SS. Thus a capacitor (C_SS) connected between SS and ground charges linearly from 0 V to 7.5 V in [0.54 × C_SS (µF)] s.

PKLMT (Peak Current Limit): Use PKLIM to establish the highest value of current to be controlled by the power MOSFET. With the resistor divider values shown in Figure 9, the 0-V threshold at PKLIM is reached when the voltage drop across the 0.25-Ω current-sense resistor is 7.5 V × 2 k / 10 k = 1.5 V, corresponding to 6 A. TI recommends a bypass capacitor from PKLIM to GND to filter out very high frequency noise.

9.2.2.2 Control Inputs

VSENSE (Output DC Voltage Sense): The threshold voltage for the VSENSE input is 7.5 V and the input bias current is typically 50 nA. The values shown in Figure 9 are for an output voltage of 400-V DC. In this circuit, the voltage amplifier operates with a constant low-frequency gain for minimum output excursions. The 47-nF feedback capacitor places a 15-Hz pole in the voltage loop that prevents 120-Hz ripple from propagating to the input current.

IAC (Line Waveform): To force the line current waveshape to follow the line voltage, a sample of the power line voltage in waveform is introduced at IAC. This signal is multiplied by the output of the voltage amplifier in the internal multiplier to generate a reference signal for the current control loop.

This input is not a voltage, but a current (hence I_AC), and is set up by the 220-kΩ and 910-kΩ resistive divider (see Figure 12). The voltage at IAC is internally held at 6 V, and the two resistors are chosen so that the current flowing into IAC varies from zero (at each zero-crossing) to about 400 µA at the peak of the waveshape. The following formulas are used to calculate these resistors:

Equation 2.

where

• V_PK is the peak line voltage

Equation 3.

ISENSE and MULTOUT (Line Current): The voltage drop across the 0.25-Ω current-sense resistor is applied to ISENSE and MULTOUT as shown. The current-sense amplifier also operates with high low-frequency gain, but unlike the voltage amplifier, it is set up to give the current-control loop a very wide bandwidth. This bandwidth enables the line current to follow the line voltage as closely as possible. In the present example, this amplifier has a zero at about 500 Hz, and a gain of about 18 dB thereafter.

VRMS (RMS Line Voltage): An important feature of the UC3854 preregulator is that it operates with a three-to-one range of input line voltages, covering everything from low line in the US (85 VAC) to high line in Europe (255 VAC). This is done using line feedforward, which keeps the input power constant with varying input voltage (assuming constant load power). To do this, the multiplier divides the line current by the square of the RMS value of the line voltage. The voltage applied to VRMS, proportional to the average of the rectified line voltage and proportional to the RMS value, is squared in the UC3854, and then used as a divisor by the multiplier block. The multiplier output, at MULTOUT, is a current that increases with the current at IAC and the voltage at VAOUT, and decreases with the square of the voltage at VRMS.

PWM Frequency: The PWM oscillator frequency in Figure 9 is 100 kHz. This value is determined by C_T at pin CT and R_SET at pin RSET. R_SET must be chosen first because it affects the maximum value of I_MULT according to the equation Equation 4.

Equation 4.

This effectively sets a maximum PWM-controlled current. With R_SET = 15 k,

Equation 5.

Also note that the multiplier output current never exceeds twice I_AC.

With the 4-kΩ resistor from MULTOUT to the 0.25-Ω current-sense resistor, the maximum current in the current-sense resistor is:

Equation 6.

Having thus selected R_SET, the current sense resistor, and the resistor from MULTOUT to the current sense resistor, calculate C_T for the desired PWM oscillator frequency from Equation 7.

Equation 7.