SLUS336A June   1998  – December 2016 UC1854 , UC2854 , UC3854

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Protection Inputs
        2. 9.2.2.2 Control Inputs
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • J|16
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DW, J, and N Packages
16-Pin SOIC, CDIP, and PDIP
Top View
FN Package
20-Pin PLCC
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME CDIP, PDIP, SOIC PLCC
CAOUT 3 4 O Current amplifier output. This is the output of a wide-bandwidth operational amplifier that senses line current and commands the pulse-width modulator (PWM) to force the correct current. This output swings close to GND, allowing the PWM to force zero duty cycle when necessary. The current amplifier remains active even if the IC is disabled. The current-amplifier output stage is an NPN emitter-follower pullup and an 8-kΩ resistor to ground.
CT 14 18 I Oscillator timing capacitor. A capacitor from CT to GND sets the PWM oscillator frequency.
Use Equation 1:
Equation 1. UC1854 UC2854 UC3854 eq2_ct_freq_slus336.gif
ENA 10 13 I Enable. ENA is a logic input that enables the PWM output, voltage reference, and oscillator. ENA also releases the soft-start clamp, allowing SS to rise. When not in use, connect ENA to a 5-V supply or pull ENA high with a 22-kΩ resistor. The ENA pin is not intended to be used as a high speed shutdown to the PWM output.
GND 1 2 — Ground. All voltages are measured with respect to GND. VCC and VREF must be bypassed directly to GND with an 0.1-µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to GND must also be as short and as direct as possible.
GTDRV 16 20 O Gate drive. The output of the PWM is a totem-pole MOSFET gate driver on GTDRV. This output is internally clamped to 15 V so that the IC operates with VCC as high as 35 V. Use a series gate resistor of at least 5 Ω to prevent interaction between the gate impedance and the GTDRV output driver that might cause the GTDRV output to overshoot excessively. Some overshoot of the GTDRV output is always expected when driving a capacitive load.
IAC 6 8 I Input AC current. This input to the analog multiplier is a current. The multiplier is tailored for very low distortion from this current input (IAC) to MULTOUT, this is the only multiplier input that must be used for sensing instantaneous line voltage. The nominal voltage on IAC is 6 V, in addition to a resistor from IAC to rectified 60 Hz, connect a resistor from IAC to REF. If the resistor to VREF is one-fourth of the value of the resistor to the rectifier, then the 6-V offset is cancelled, and the line current has minimal cross-over distortion.
ISENSE 4 5 I Current-sense minus. This is the inverting input to the current amplifier. This input and the non-inverting input, MULTOUT, remain functional down to and below GND. Take care to avoid taking these inputs below –0.5 V because they are protected with diodes to GND.
MULTOUT 5 7 I/O Multiplier output and current-sense plus. The output of the analog multiplier and the non-inverting input of the current amplifier are connected together at MULTOUT. The cautions about taking ISENSE below –0.5 V also apply to MULTOUT. As the multiplier output is a current, this is a high-impedance input similar to ISENSE, so the current amplifier can be configured as a differential amplifier to reject GND noise. Figure 9 shows an example of using the current amplifier differentially.
NC — 1, 6, 11, 16 — No connection
PKLMT 2 3 I Peak current limit. The threshold for PKLMT is 0 V. Connect this input to the negative voltage on the current-sense resistor as shown in Figure 9. Use a resistor to VREF to offset the negative current-sense signal up to GND.
RSET 12 15 I Oscillator charging current and multiplier limit set. A resistor from RSET to GND programs oscillator charging current and maximum multiplier output. Multiplier output current does not exceed 3.75 V divided by the resistor from RSET to GND.
SS 13 17 I Soft start. SS remains at GND as long as the device is disabled or VCC is too low. SS pulls up to over 8 V by an internal 14-mA current source when both VCC becomes valid and the IC is enabled. SS acts as the reference input to the voltage amplifier if SS is below VREF. With a large capacitor from SS to GND, the reference to the voltage regulating amplifier rises slowly, and increases the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS quickly discharges to ground and disables the PWM.
VAOUT 7 9 O Voltage amplifier output. This is the output of the operational amplifier that regulates output voltage. Like the current amplifier, the voltage amplifier remains active even if the IC is disabled with either ENA or VCC. This means that large feedback capacitors across the amplifier stay charged through momentary disable cycles. Voltage amplifier output levels below 1 V inhibit multiplier output. The voltage amplifier output is internally limited to approximately 5.8 V to prevent overshoot. The voltage amplifier output stage is an NPN emitter-follower pullup and an 8-kΩ resistor to ground.
VCC 15 19 — Positive supply voltage. Connect VCC to a stable source of at least 20 mA above 17 V for normal operation. Also bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate GTDRV signals, these devices are inhibited unless VCC exceeds the upper undervoltage-lockout threshold and remains above the lower threshold.
VREF 9 12 O Voltage reference output. VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 10 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when VCC is low or when ENA is low. Bypass VREF to GND with an 0.1-µF or larger ceramic capacitor for best stability.
VRMS 8 10 I RMS line voltage. The output of a boost PWM is proportional to the input voltage, so when the line voltage into a low-bandwidth boost PWM-voltage regulator changes, the output changes immediately and slowly recovers to the regulated level. For these devices, the VRMS input compensates for line voltage changes if it is connected to a voltage proportional to the RMS input line voltage. For best control, the VRMS voltage must stay between 1.5 V and 3.5 V.
VSENSE 11 14 I Voltage amplifier inverting input. This is normally connected to a feedback network and to the boost converter output through a divider network.