JAJSK41A January   2021  – June 2021 UCC12051-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 UVLO, Power-Up, and Power-Down Behavior
      3. 7.3.3 VISO Load Recommended Operating Area
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 External Clocking and Synchronization
      6. 7.3.6 VISO Output Voltage Selection
      7. 7.3.7 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VISO Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4 Thermal Information

THERMAL METRIC(1)UCC12051-Q1UNIT
DVE (SOIC)
16 PINS
RθJAJunction-to-ambient thermal resistance57.5°C/W
RθJC(top)Junction-to-case (top) thermal resistance21.6°C/W
RθJBJunction-to-board thermal resistance33.8°C/W
ψJTJunction-to-top characterization parameter10.2°C/W
ψJBJunction-to-board characterization parameter33.7°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance—°C/W
(1) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board when PDP = 129 mW, PDS = 142 mW and PDT = 129 mW. The board temperature is taken from Pin 12. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.