JAJSK41A January   2021  – June 2021 UCC12051-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 UVLO, Power-Up, and Power-Down Behavior
      3. 7.3.3 VISO Load Recommended Operating Area
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 External Clocking and Synchronization
      6. 7.3.6 VISO Output Voltage Selection
      7. 7.3.7 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VISO Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 DVE Package16-Pin SOICTop View
Table 5-1 Pin Functions
PIN TYPE (1) DESCRIPTION
NAME NO.
EN 1 I Enable pin. Forcing EN low disables the device. Pull high to enable normal device functionality.
GNDP 2 P Power ground return connection for VINP.
GNDS 9 P Connect to GNDS plane on printed circuit board. Do not use as only ground connection for VISO. Ensure pin 15 is connected to circuit ground.
16
GNDS 15 P Secondary side ground return connection for VISO. Connect bypass capacitor from VISO to this pin.
NC 6 — Pins internally connected together. No other electrical connection. Pins belong to primary-side voltage domain. Connect to GNDP on printed circuit board.
7
8
10 — No internal connection. Pin belongs to isolated voltage domain. Connect to GNDS on printed circuit board.
11
12
SYNC 4 I Synchronous clock input pin. Provide a clock signal to synchronize multiple devices or connect to GNDP for standalone operation using the internal oscillator. If the SYNC pin is left open make sure to it separate it from any switching noise to avoid false clock coupling.
SYNC_OK 5 O Active-low, open-drain diagnostic output. Pin is asserted LOW if there is no external SYNC clock or one that is outside of the operating range of the is detected. In this state, the external clock is ignored and the DC/DC converter is clocked by the internal oscillator. The pin is in high-impedance if a clock is applied on SYNC.
SEL 13 I VISO selection pin. VISO setpoint is 5.0 V when SEL is shorted to VISO, 5.4 V when SEL is connected to VISOthrough a 100-kΩ resistor, 3.3 V when SEL is shorted to GNDS, and 3.7 V when SEL is connected to GNDS through a 100-kΩ resistor. For more information see the Section 7.4 section.
VINP 3 P Primary side input supply voltage pin. A 10-μF ceramic capacitor to GNDP on pin 2, placed close to the device pins, is required.
VISO 14 P Isolated supply voltage pin. A 10-μF ceramic capacitor to GNDS on pin 15, placed close to the device pins, is required. See Section 8.2.2.1 section.
(1) P = Power, G = Ground, I = Input, O = Output