JAJSO45A August 2023 – September 2023 UCC14130-Q1
PRODUCTION DATA
UCC1413x-Q1 power-up diagram of two output rails with soft start is shown in Figure 11-5. After VVIN > VVIN_UVLOP and ENA is pulled high, the soft-start sequence starts with burst duty cycle control with soft duty cycle increment. The burst duty cycle gradually increases from 12.5% to 50% over time by the primary-side control signal (DSS_PRI), so both VVDD-VEE and VCOM-VEE increase ratiometrically with a controlled shallow rising slope. When VVDD-VEE is increased above VVDD_UVLOS, there is a sufficient bias voltage for the feedback-loop communication channel, so the burst feedback control on the secondary side takes over. As a result, the DSS_PRI is pulled high and does not affect burst duty cycle anymore. The burst duty cycle is determined by comparing VFBVDD and VREF. VREF increases from 0.9V to 2.5 V with seven increment steps, where the first 1-V step boosts VREF from 0.9V to 1.9V, and then the following six 0.1-V steps boosts VREF from 1.9V to 2.5V. Each step lasts 128 µs. After VVDD-VEE > VVDD_UVP, the RLIM source-sink regulator for VCOM-VEE is enabled. The polarity of source or sink current of RLIM pin is determined by comparing VFBVEE and VREF so as to keep VCOM-VEE in tight regulation. Once VVDD-VEE or VCOM-VEE rises across its UVP threshold, there is a 3-ms (typical) deglitch time for VVDD-VEE UVP and VCOM-VEE UVP and OVP, and then the power good signal is issued by pulling PG voltage low. The 3-ms (typical) deglitch time is only applied during start up before the power good signal is issued. It provides enough time for both VVDD-VEE and VCOM-VEE to settle in their hysteresis band of regulation after start up, so that the converter does not shut down due to the overshoot or undershoot during start up.
The soft-start feature greatly reduces the input inrush current during power-up. In addition, if VVDD-VEE cannot reach to VVDD_UVLOS within tSOFT_START_TIME_OUT, then the device shuts down in a safe-state. The soft-start time-out protects the module under output short circuit condition or over-load during power up.