JAJSO45A August   2023  – September 2023 UCC14130-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. 8 Safety-Related Certifications
  10. 9 Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 機能ブロック図
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
    3. 12.3 System Examples
  14. 13Power Supply Recommendations
  15. 14Layout
    1. 14.1 Layout Guidelines
    2. 14.2 Layout Example
  16. 15デバイスおよびドキュメントのサポート
    1. 15.1 ドキュメントのサポート
      1. 15.1.1 関連資料
    2. 15.2 ドキュメントの更新通知を受け取る方法
    3. 15.3 サポート・リソース
    4. 15.4 商標
    5. 15.5 静電気放電に関する注意事項
    6. 15.6 用語集
  17. 16Mechanical, Packaging, and Orderable Information
  18. 17Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12.3 System Examples

The UCC1413x-Q1 module is designed to allow a microcontroller host to enable it with the ENA pin for proper system sequencing. The PG output also allows the host to monitor the status of the module. The PG pin goes low when there are no faults and the output voltage is within ±10% of the set target output voltage. The output voltage can be used to power a gate driver for either GaN, IGBT or SiC FET power devices. The host can start sending PWM control to the gate driver after the PG pin goes low to ensure proper sequencing. Shown below is the system diagram for the dual-output configuration and a system diagram for the single output configuration.

GUID-BE4DD983-ACB1-4CDA-9A11-660D3293B748-low.svgFigure 12-11 Dual Output System Configuration

GUID-FE9A506B-4E61-4962-9D28-A8501BF46CC0-low.svgFigure 12-12 Single Output System Configuration