UCC14140-Q1 power-up diagram of two output rails with soft start is shown in Figure 8-5. After V_VIN > V_{VIN_UVLOP} and ENA is pulled high, the soft-start sequence starts with burst duty cycle control with soft duty cycle increment. The burst duty cycle gradually increases from 12.5% to 50% over time by the primary-side control signal (D_{SS_PRI}), so both V_VDD-VEE and V_COM-VEE increase ratiometrically with a controlled shallow rising slope. When V_VDD-VEE is increased above V_{VDD_UVLOS}, there is a sufficient bias voltage for the feedback-loop communication channel, so the burst feedback control on the secondary side takes over. As a result, the D_{SS_PRI} is pulled high and does not affect burst duty cycle anymore. The burst duty cycle is determined by comparing V_FBVDD and V_REF. V_REF increases from 0.9V to 2.5 V with seven increment steps, where the first 0.4-V step boosts V_REF from 0.9V to 1.3V, and then the following six 0.2-V steps boosts V_REF from 1.3V to 2.5V. Each step lasts 128 µs. After V_VDD-VEE > V_{VDD_UVP}, the RLIM source-sink regulator for V_COM-VEE is enabled. The polarity of source or sink current of RLIM pin is determined by comparing V_FBVEE and V_REF so as to keep V_COM-VEE in tight regulation. Once V_VDD-VEE or V_COM-VEE rises across its UVP threshold, there is a 3-ms (typical) deglitch time for V_VDD-VEE UVP and V_COM-VEE UVP and OVP, and then the power good signal is issued by pulling PG voltage low. The 3-ms (typical) deglitch time is only applied during start up before the power good signal is issued. It provides enough time for both V_VDD-VEE and V_COM-VEE to settle in their hysteresis band of regulation after start up, so that the converter does not shut down due to the overshoot or undershoot during start up.

The soft-start feature greatly reduces the input inrush current during power-up. In addition, if V_VDD-VEE cannot reach to V_{VDD_UVLOS} within 28.4 ms, then the device shuts down in a safe-state. The 28.4-ms soft-start time-out protects the module under output short circuit condition before power up.

Figure 8-5 Output voltage Soft-Start Diagram