JAJSQN3 june   2023  – june 2023 UCC14140-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Insulation Specifications
    6. 7.6  Safety-Related Certifications
    7. 7.7  Electrical Characteristics
    8. 7.8  Safety Limiting Values
    9. 7.9  Insulation Characteristics
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Stage Operation
        1. 8.3.1.1 VDD-VEE Voltage Regulation
        2. 8.3.1.2 COM-VEE Voltage Regulation
        3. 8.3.1.3 Power Handling Capability
      2. 8.3.2 Output Voltage Soft Start
      3. 8.3.3 ENA and PG
      4. 8.3.4 Protection Functions
        1. 8.3.4.1 Input Undervoltage Lockout
        2. 8.3.4.2 Input Overvoltage Lockout
        3. 8.3.4.3 Output Undervoltage Protection
        4. 8.3.4.4 Output Overvoltage Protection
        5. 8.3.4.5 Overpower Protection
        6. 8.3.4.6 Overtemperature Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Capacitor Selection
        2. 9.2.2.2 Single RLIM Resistor Selection
        3. 9.2.2.3 RDR Circuit Component Selection
    3. 9.3 System Examples
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Electrical Characteristics

Over operating temperature range (TJ = –40 °C to 150 °C), VVIN = 8 V to 18 V, CIN = 20 µF, COUT = 10 µF, RLIM = 1 kΩ, VENA = 5 V, unless otherwise noted. All typical values at TA = 25 °C and VVIN = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (Primary-side. All voltages with respect to GNDP)
VVIN Input voltage range, 0.7W@(VDD-VEE)=25V, TA=85oC Primary-side input voltage to GNDP 8(1) 12 18 V
Input voltage range, 1.2W@(VDD-VEE)=25V, TA=85oC Primary-side input voltage to GNDP 11.4 12 12.6 V
IVINQ_OFF VIN quiescent current, disabled VENA = 0 V; VVIN = 8 V-18 V;  600 µA
IVIN_ON_NO_LOAD VIN operating current, enabled, No Load VENA = 5 V; VVIN = 8 V-18 V; (VDD-VEE) = 25 V regulating; IVDD-VEE = 0 mA. Single Output. 40 mA
IVIN_ON_FULL_LOAD VIN operating current, enabled, Full Load VENA = 5 V; VVIN = 8 V-18 V; (VDD-VEE) = 25-V regulating; IVDD-VEE = 40 mA. Single Output. 200 mA
VIN operating current, enabled, Full Load VENA = 5 V; VVIN =11.4 V-12.6 V; (VDD-VEE) = 25-V regulating; IVDD-VEE = 60 mA. Single Output. 270 mA
UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVIN_UVLOP_RISING VIN analog undervoltage lockout rising threshold Analog Comparator Always Active First 7.8 8.2 8.5 V
VVIN_ UVLOP_FALLING VIN analog undervoltage lockout falling threshold Analog Comparator Always Active First 7 7.4 7.7 V
OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVIN_OVLO_RISING VIN overvoltage lockout rising threshold 20.9 22 23.1 V
VVIN_OVLO_FALLING VIN overvoltage lockout falling threshold 19 20 21 V
TSHUTP THERMAL SHUTDOWN COMPARATOR (Primary-side. All voltages with respect to GNDP)
TSHUTPPRIMARY_RISING Primary-side over-temperature shutdown rising threshold First time at power-up TJ needs to be < 140 °C to turnon 150 160 170 °C
TSHUTPPRIMARY_HYST Primary-side over-temperature shutdown hysteresis 15 20 25 °C
ENA INPUT PIN (Primary-side. All voltages with respect to GNDP)
VEN_IR Input voltage rising threshold, logic HIGH Rising edge 2.1 V
VEN_IF Input voltage falling threshold, logic LOW Falling edge 0.8 V
IEN Enable Pin Input Current VENA = 5.0 V 5 10 µA
PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP)
VPG_OUT_LO PG output-low saturation voltage Sink Current = 5 mA, power good 0.5 V
IPG_OUT_HI PG Leakage current VPG = 5.5 V, power not good 5 µA
Primary-side Control (All voltages with respect to GNDP)
FSW Switching frequency VVIN = 12 V; VENA = 5 V; (VDD-VEE) = 25 V 16 MHz
FSSM Frequency of Spread Spectrum Modulation (SSM) triangle waveform Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; FSS_BURST_P = 125 kHz 90 kHz
SSM Percentage change of FCARRIER SSM Percent change of carrier frequency during Spread Spectrum Modulation (SSM) by triangle waveform Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; FSS_BURST_P  = 125 kHz 5 %
tSOFT_START_TIME_OUT Primary-side soft-start time-out Timer begins when VIN > UVLOP and ENA = High and reset when Powergood pin indicates Good  28.4 ms
(VDD-VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVDD_RANGE (VDD – VEE) Output voltage range 15 25 V
VVDD_DC_ACCURACY (VDD – VEE) Output voltage DC regulation accuracy
Secondary-side (VDD – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider, within SOA range.
 		 -1.3 1.3 %
(VDD-VEE) REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
VFBVDD_REF Feedback regulation reference voltage for (VDD – VEE) (VDD – VEE) output in regulation 2.4675 2.5 2.5325 V
VFBVDD_HYSTCMP_HYST (VDD-VEE) Hysteresis comparator hysteresis settings.
Hysteresis at the VFBVDD pin.		 Hysteresis Setting 9 10 12.3 mV
(COM-VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVEE_RANGE (COM – VEE) Output voltage range Secondary-side (COM – VEE), adjust with external resistor divider 2.5 (VDD-VEE) V
VVEE_DC_ACURACY
(COM - VEE)
Output voltage DC
regulation accuracy

 
Secondary-side (COM – VEE)
output voltage, over load, line and temperature range, externally adjust with external resistor
divider		 –1.3 1.3 %
(COM-VEE) REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
VFBVEE_REF Feedback regulation reference voltage for (COM – VEE) (COM – VEE) output in regulation 2.4675 2.5 2.5325 V
VRLIM_SHORT_CHRG_CMP_RISE Rlim Short Charge comparator rising threshold to exit PWM Rising threshold 0.73 V
tRLIM_SHORT_CHRG_ON_TIME On-Time during RLIM pin Short Charge PWM mode RLIM pin < 0.645 V, while FBVEE pin < 2.48 V 1.1 us
tRLIM_SHORT_CHRG_OFF_TIME Off-Time during RLIM pin Short Charge PWM mode RLIM pin < 0.645 V, while FBVEE pin < 2.48 V 5 us
(VDD-VEE) UVLOs COMPARATOR (Secondary-side. All voltages with respect to VEE) 
VVDD_UVLOS_RISING (VDD – VEE) undervoltage lockout rising threshold Voltage at FBVDD 0.9 V
VVDD_UVLOS_HYST (VDD – VEE) undervoltage lockout hysteresis Voltage at FBVDD 0.2 V
(VDD-VEE) OVLOs COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVDD_OVLOS_RISING (VDD – VEE) over-voltage lockout rising threshold Voltage from VDD to VEE, rising 29.45 31 32.55 V
VVDD_OVLOS_FALLING (VDD – VEE) over-voltage lockout falling threshold Voltage from VDD to VEE, falling 27.55 29 30.45 V
SOFT-START (Secondary-side. All voltages with respect to VEE)
tdeglitch Deglitch time during soft start before PG for (VDD-VEE) UVP and (COM-VEE) UVP & OVP 3 ms
(VDD-VEE) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVDD_UVP_RISING (VDD – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% 2.175 2.25 2.35 V
VVDD_UVP_HYST (VDD – VEE) under-voltage protection hysteresis 20 mV
(VDD-VEE) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVDD_OVP_RISING (VDD – VEE) over-voltage protection rising threshold, VOVP = VREF ×110% 2.7 2.75 2.825 V
VVDD_OVP_HYST (VDD – VEE) over-voltage protection hysteresis 20 mV
(COM-VEE) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVEE_UVP_RISING (COM – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% 2.1 2.25 2.4 V
VVEE_UVP_HYST (COM – VEE) under-voltage protection hysteresis 20 mV
(COM-VEE) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVEE_OVP_RISING (COM – VEE) over-voltage protection rising threshold, VOVP = VREF × 110% 2.7 2.75 2.825 V
VVEE_OVP_HYST (COM – VEE) over-voltage protection hysteresis 20 mV
TSHUTS THERMAL SHUTDOWN COMPARATOR (Secondary-side. All voltages with respect to VEE)
TSHUTSSECONDARY_RISE Secondary -side over-temperature shutdown rising threshold First time at power-up Tj needs to be < 140oC to turnon. 150 160 170 °C
TSHUTSSECONDARY_HYST Secondary-side over-temperature shutdown hysteresis 15 20 25 °C
CMTI (Common Mode Transient Immunity)
CMTI Common Mode Transient Immunity Positive VEE with respect to GNDP 150 V/ns
Negative VEE with respect to GNDP -150 V/ns
INTEGRATED MAGLAM TRANSFORMER (Primary-side to Secondary-side. Note: these values unique for each version of XFMR)
N Transformer effective turns ratio Secondary side to primary side 2.72 -
(1) See the VVIN_UVLOP_RISING and VVIN_ UVLOP_FALLING electrical characteristics for the miminum operational VVIN. Becasue VVIN_ UVLOP_FALLING < 8V, VVIN can operate at 8V as long as VVIN > VVIN_UVLOP_RISING during start up.