JAJSQ36A april   2023  – august 2023 UCC14241-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. Safety-Related Certifications
  10. Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
      3. 12.2.3 Application Curves
    3. 12.3 System Examples
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Power Handling Capability

The maximum power handling capability is determined by both circuit operation and thermal condition. For a given output voltage, the maximum power increases with input voltage before triggering the thermal protection. An over-power-protection (OPP) is implemented to limit maximum output power and reduces power stage RMS current at high input voltage. The OPP is implemented by a feed-forward control from the input voltage to the OPP burst duty cycle (DOPP). The DOPP adds a "baby" burst within the on-time of "Mama" burst from the main feedback loop for the (VDD-VEE) regulation. When the input voltage increases, the DOPP reduces automatically to limit the averaged output power.

At high ambient temperature, the thermal performance determines the maximum power and safe operating area (SOA). A protective thermal shut-down is triggered after overtemperature is detected. The high-efficiency and optimized thermal design for transformer and silicon provide a high power handling capability at high ambient temperature in a small package.

GUID-0EFC80B9-ACF8-4CAC-9E73-DCDE887DC552-low.svg Figure 11-4 Diagram of Over-Power-Protection with baby burst