JAJSQ36A april   2023  – august 2023 UCC14241-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. 8 Safety-Related Certifications
  10. 9 Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
      3. 12.2.3 Application Curves
    3. 12.3 System Examples
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.3.1.2 COM-VEE Voltage Regulation

COM-VEE output takes VDD-VEE output as its input and creates a regulated output voltage. It can be considered as an LDO output from VDD-VEE, though the operation principle is not quite the same. Given its input voltage is VDD-VEE, the maximum output voltage from COM to VEE is the voltage between VDD and VEE.

The COM-VEE output regulator stage uses the internal high-side or low-side FETs in series with the external current-limit resistor (RLIM) to charge or discharge the COM-VEE output voltage. The hysteresis control is used to control the switching instance of the two FETs, to achieve an accurately regulated COM-VEE voltage. As shown in Figure 11-2, the COM-VEE output voltage is sensed through the voltage divider RFBVEE_TOP and RFBVEE_BOT on FBVEE pin. TI recommends a 330-pF capacitor on FBVEE pin to filter out the switching frequency noise. When the voltage on FBVEE is below the charging threshold, 20 mV below the VFBVEE_REF, the charging resistor is kept on and discharging resistor is kept off. COM-VEE output voltage rises. After FBVEE voltage reaches the stop charging threshold, 20 mV above the VFBVEE_REF, the charging resistor is turned off. Output voltage rise stops. When the charging resistor is turned off, the discharge resistor is controlled by another hysteresis controller, based on FBVEE pin voltage, with the same reference voltage VFBVEE_REF, and 20-mV of hysteresis.

The COM-VEE output regulator stage will protect from having the high-side FET stay ON for a long time during a COM to VEE short. This protection feature is implemented by monitoring the RLIM-pin voltage and controlling the high-side FET duty-ratio. When the COM pin voltage is lower than 0.645 V while the FBVEE voltage is below 2.48 V, the hysteretic control of the COM-VEE regulator is overridden by an approximately 20 % duty-ratio control on high-side FET, with a typical on-time of tRLIM_SHORT_CHRG_ ON_TIME and off-time of tRLIM_SHORT_CHRG_ OFF_TIME in each duty cycle. When the COM pin voltage is higher than VRLIM_SHORT_CHRG_CMP_RISE, the duty ratio control is disabled and the hysteretic control resumes to normal operation.

GUID-C2E4C3DE-7559-484B-A720-45BCBC7F6034-low.svgFigure 11-2 COM-VEE Voltage Regulation
GUID-2A88DFB8-DDE2-4E95-81A5-07FD2302B498-low.svgFigure 11-3 COM-VEE Voltage Regulation Diagram