JAJSQ36 データシート

JAJSQ36A april 2023 – august 2023 UCC14241-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DWN|36
- MPSS132

サーマルパッド・メカニカル・データ

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jajsq36a_oa

12.2.2.1 Capacitor Selection

The UCC14241-Q1 device creates an isolated output VDD-VEE as its main output. The device also creates a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and sharing VEE as the common reference point, the UCC14241-Q1 outputs can be configured as dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative. UCC14241-Q1 output can also be used as a single positive output or single negative output.

When the module is configured as dual-output, one-positive output, one-negative output; it is very important to properly select the output capacitor ratios C_OUT2 and C_OUT3 to optimize the regulation and avoid causing an over-voltage or under-voltage fault.

Table 12-2 Calculated Capacitor Values

CAPACITOR	VALUE (µF)	NOTES
C_IN	10 + 0.1	Place a 10-μF and a 0.1-μF high-frequency decoupling capacitor in parallel close to VIN pins. A capacitance greater than 10 uF can be used to reduce the voltage ripple when the series impedance from the voltage source to the VIN pins is large.
C_OUT1	2.2+ 0.1	Add a 2.2-μF and a 0.1-μF capacitor for high-frequency decoupling of (VDD – VEE). Place close to the VDD and VEE pins. A capacitance greater than 2.2 uF can be used to reduce the output voltage ripple.
C_OUT1B	See below	Bulk charge, decoupling output capacitors are required to be located next to the gate driver pins. The C_OUT2 and C_OUT3 capacitance ratio is important to optimize the dual output voltage divider accuracy during charge or discharge switching cycles; while the C_OUT1B capacitor is used to minimize the total capacitance including C_OUT1B, C_OUT2, and C_OUT3 capacitance values.
C_OUT2	See below
C_OUT3	See below

Output capacitor decoupling is important for optimal gate driver operation. Best high frequency decoupling can be achieved by reducing the parasitic impedance in the charge/discharge path. Using ceramic capacitors with low ESR and low ESL are important, as well as minimizing the trace impedance.

As described in Figure 12-3, a decoupling capacitor C_OUT1 is required at the V_VDD-VEE output pins of the UCC14241-Q1 for high frequency decoupling. C_OUT2 and C_OUT3 however, are needed at the gate driver pins for V_VDD-COM and V_VEE-COM decoupling. The impedance between C_OUT1 and the C_OUT2/C_OUT3 combo prevents the C_OUT1 from assisting the high frequency decoupling of the gate driver, requiring the C_OUT2 and C_OUT3 to take on the full load. The impedance may be contributed from the PCB traces, socket connections, EMI filters, or ferrite beads etc. This causes the C_OUT2 and in particular the C_OUT3 to get relatively large achieve a small voltage droop.

Figure 12-3 Dual Output Schematic with C_out1, C_out2, and C_out3

The required C_OUT2 and C_OUT3 capacitance can be reduced by introducing a C_OUT1B capacitor from V_VDD-VEE at the gate driver pins next to C_OUT2 and C_OUT3 as shown in Figure 12-4. The C_OUT1B assists with the decoupling total capacitance for both C_OUT2 and C_OUT3; thereby reducing the total capacitance (C_OUT1B + C_OUT2 +C_OUT3) needed to achieve the desired voltage droop. Figure 12-5 shows that as C_OUT1B is increased from “none” to higher C_OUT1B values, there is a significant reduction in C_OUT2 and C_OUT3 and reduction of the total net capacitance, until a point of diminishing returns is reached (a “knee” point) where any additional C_OUT1B will have a relatively small reduction of C_OUT2 and C_OUT3, and starts more significantly increasing the total net capacitance. The optimal C_OUT1B, C_OUT2, and C_OUT3 at the minimum total net capacitance benefit both output capacitor size reduction and BOM cost reduction.

Figure 12-4 Dual Output Schematic with C_out1, C_out1B, C_out2, and C_out3

Figure 12-5 Output Capacitance variation with C_out1B selection

To calculate C_OUT1B, C_OUT2, and C_OUT3, we calculate the equivalent (VDD-COM) capacitance, which is equal to the series capacitance of C_OUT1B and C_OUT3 in parallel with C_OUT2. This equivalent (VDD-VEE) capacitance will be sized to limit the predetermined (VDD-COM) discharge voltage drop when the power switch (SiC or IGBT) gate charge is turned-on.

Equation 1.

C_{{(VDD-COM)}_{EQ}} = \frac{C_{OUT1B} × C_{OUT3}}{C_{OUT1B} + C_{OUT3}} + C_{OUT2}

Solving for acceptable voltage droop on V_VDD-COM from the load transient, ∆V_{(VDD-COM)_droop},

Equation 2.

C_{{(V D D - C O M)}_{E Q}} = \frac{Q_{g}}{{∆ V}_{(V D D - C O M)_d r o o p}}

The C_OUT2 over C_OUT3 ratio is defined as a coefficient of K₂₃,which is the multiplication of a voltage divider ratio along with a ratio of differential current. The voltage divider ratio is from the series configuration of the two capacitors. The current divider ratio is calculated based on the charge current through the two capacitors. I_{MAX_POWER} is the maximum instantaneous current from the power module during the burst on-time, which can be obtained from dividing the maximum power on the datasheet SOA curve at T_A of 25°C by V_VDD-VEE. I_VDD-COM is the total quiescent current between VDD and COM. For gate driver as example, I_VDD-VEE is the current consumption without switching. I_COM-VEE is the total quiescent current between COM and VEE. Based on KCL, the differential current charging up C_OUT2 during the burst on-time is (I_{MAX_POWER} - I_VDD-COM), and the one charging up C_OUT3 is (I_{MAX_POWER} - I_COM-VEE).

Equation 3.

C_{O U T 3} = C_{O U T 2} \times K_{23}

where

Equation 4.

K_{23} = \frac{V_{(V D D - C O M)} \times (I_{M A X_P O W E R} - I_{C O M - V E E})}{V_{(C O M - V E E)} \times (I_{M A X_P O W E R} - I_{V D D - C O M})}

Next, plugging the above C_OUT3 expression into the Equation 1 we get

Equation 5.

\frac{Q_{g}}{{∆ V}_{(V D D - C O M)_d r o o p}} = \frac{C_{O U T 1 B} \times (C_{O U T 2} \times K_{23})}{C_{O U T 1 B} + (C_{O U T 2} \times K_{23})} + C_{O U T 2}

The total decoupling capacitance close to the point of load (C_{OUT_Total}) is the summation of C_OUT1B, C_OUT2 and C_OUT3. The goal is to find a smallest C_OUT1B to reduce C_{OUT_Total} to the minimum for BOM cost and footprint saving, while retaining the desired load transient performance. The optimal C_OUT1B can be calculated by solving the partial derivative of C_{OUT_Total} equal to 0.

Equation 6.

\frac{d C_{O U T_T o t a l}}{d C_{O U T 1 B}} = \frac{d}{d C_{O U T 1 B}} (C_{O U T 1 B} + C_{O U T 2} + C_{O U T 3}) = 0

Including the above C_OUT3 and C_OUT2 expressions onto Equation 6, the optimal C_OUT1B is derived as

Equation 7.

C_{O U T 1 B} = \frac{K_{23} \times Q_{g} \times ({K_{23}}^{3} + \sqrt{{K_{23}}^{2} + K_{23} + 1} + {K_{23}}^{2} \times \sqrt{{K_{23}}^{2} + K_{23} + 1} - 1)}{{∆ V}_{(V D D - C O M)_d r o o p} \times {(K_{23} + 1)}^{2} \times ({K_{23}}^{2} + K_{23} + 1)}

After that, solving Equation 5 including Equation 7, C_OUT2 can be solved as

Equation 8.

C_{O U T 2} = \frac{K_{23} \times Q_{g} - (1 + K_{23}) \times C_{O U T 1 B} \times {∆ V}_{{(V D D - C O M)}_{d r o o p}}}{2 \times K_{23} \times {∆ V}_{(V D D - C O M)_d r o o p}} + \frac{\sqrt{C_{O U T 1 B}^{2} {∆ V}_{{(V D D - C O M)}_{d r o o p}}^{2} ({K_{23}}^{2} + 2 K_{23} + 1) + 2 C_{O U T 1 B} K_{23} Q_{g} {∆ V}_{{(V D D - C O M)}_{d r o o p}} (1 - K_{23}) + {K_{23}}^{2} Q_{g}^{2}}}{2 \times K_{23} \times {∆ V}_{(V D D - C O M)_d r o o p}}

Overall, the design procedure of the three decoupling capacitors starts with C_OUT1B calculation, followed by C_OUT2 and then C_OUT3 calculation. The final capacitor values will be used to calculate R_LIM, as described in the next section.