JAJSR37A August 2023 – September 2023 UCC14340-Q1
PRODUCTION DATA
The UCC14340-Q1 module is designed to allow a microcontroller host to enable it with the ENA pin for proper system sequencing. The PG output also allows the host to monitor the status of the module. The PG pin goes low when there are no faults and the output voltage is within ±10% of the set target output voltage. The output voltage is meant to power a gate driver for either IGBT or SiC FET power device. The host can start sending PWM control to the gate driver after the PG pin goes low to ensure proper sequencing. The below figures are the system diagrams for the dual-output configuration and for the single output configuration.