JAJSR37A August   2023  – September 2023 UCC14340-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Safety-Related Certifications
    7. 7.7 Electrical Characteristics
    8. 7.8 Safety Limiting Values
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 機能ブロック図
    3. 8.3 Feature Description
      1. 8.3.1 Power Stage Operation
        1. 8.3.1.1 VDD-VEE Voltage Regulation
        2. 8.3.1.2 COM-VEE Voltage Regulation
        3. 8.3.1.3 Power Handling Capability
      2. 8.3.2 Output Voltage Soft Start
      3. 8.3.3 ENA and PG
      4. 8.3.4 Protection Functions
        1. 8.3.4.1 Input Undervoltage Lockout
        2. 8.3.4.2 Input Overvoltage Lockout
        3. 8.3.4.3 Output Undervoltage Protection
        4. 8.3.4.4 Output Overvoltage Protection
        5. 8.3.4.5 Overpower Protection
        6. 8.3.4.6 Overtemperature Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Capacitor Selection
        2. 9.2.2.2 Single RLIM Resistor Selection
        3. 9.2.2.3 RDR Circuit Component Selection
        4. 9.2.2.4 Feedback Resistors Selection
  11. 10System Examples
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1.1 VDD-VEE Voltage Regulation

The VDD-VEE output is the main output of the module. The power stage operation is determined by the sensed VDD-VEE voltage on FBVDD pin. As shown in Figure 8-1, the VDD-VEE voltage is sensed through a voltage divider RFBVDD_TOP and RFBVDD_BOT. When FBVDD voltage stays below the turn-off threshold, roughly 10 mV above the VFBVDD_REF, the power stage operates, delivers power to the secondary side and makes the VDD-VEE output voltage rise. After the output reaches the turn-off threshold, the power stage turns off. Output voltage drops because of the load current. After the output voltage drops below the turn-on threshold, roughly 10 mV below the VFBVDD_REF, the power stage is turned on again. With the accurate voltage reference and hysteresis control, the VDD-VEE output voltage can be regulated with high accuracy. To improve the noise immunity, a small capacitor of 330 pF should be added between FBVDD and VEE pins. Excessive capacitor slows down the hysteresis loop and can cause excessive output voltage ripple or even stability issue.

GUID-1F66B73A-9A5A-45C1-85B3-BF8A35E88AB1-low.svgFigure 8-1 VDD-VEE Voltage Regulation