The UCC14341-Q1 device creates an isolated output VDD-VEE as its main output. It also creates a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and sharing VEE as the common reference point, the UCC14341-Q1 outputs can be configured as dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative, as shown in Figure 8-6.

When the module is configured as dual-positive or dual-negative outputs, the R_LIM resistor is a true current limiting resistor. Set up the R_LIM resistor value as the maximum load current needed for V_OUT2, using Equation 15. I_{VOUT2_max} is the maximum load current for V_OUT2 output.

R_{LIM_INT} is the internal switch resistance value of 30Ω typical.

For isolated gate driver applications, one positive and one negative outputs are needed. In this case, VDD-VEE is the total output voltage, and the middle point becomes the reference point. Because the total voltage between VDD and VEE is always regulated through the FBVDD feedback, the RLIM pin only must regulate the middle point voltage so that it can give the correct positive and negative voltages. The RLIM control is achieved through FBVEE pin as described in COM-VEE Voltage Regulation.

Based on UCC14341-Q1 車載用 1.5W、15V V_IN、25V V_OUT、高密度、
> 5kV_RMS、絶縁型 DC/DC モジュールPower Stage OperationOutput Voltage Soft Start ENA and PG Capacitor SelectionSingle R_LIM Resistor SelectionRDR Circuit Component SelectionFeedback Resistors Selection, when selecting the output capacitor ratio proportional to the voltage ratio, the capacitors form a voltage divider. The middle point voltage must naturally give the correct positive and negative voltages. At the same time, for the gate driver circuit, the gate charge pulled out from the positive rail capacitor during turn-on is fed back to the negative rail capacitor during turn-off, the two output rail load must always be balanced. However, due to the gate driver circuit quiescent current unbalancing, and the two-rail capacitance tolerances, the middle point voltage can move away with time. The RLIM pin provides an opposite current to keep the middle point voltage at the correct level.

As illustrated in Figure 8-7 (a), without considering the gate charge, the gate driver circuit quiescent current loads the positive rail and negative rail differently. The net current shows up as a DC offset current to the middle point.

As illustrated in Figure 8-7 (b), every time the gate driver circuit turns-on the main power switch, it pulls the charge out of the positive and negative rail output capacitors. When the module power stage provides energy to the secondary side, refreshing those capacitors, the same charge is fed into both capacitors. If the capacitor values are perfect, the voltage rise in the capacitors will be proportional. The positive and negative voltages would not change. However, due to the capacitor tolerances, the capacitor values are not perfectly matched. The voltages will rise at different ratios with the smaller capacitor rising faster. Over time, the middle point voltage, COM, would pull to a different value. A load across one of the capacitors will pull towards a voltage imbalance. The RLIM function counteract the voltage imbalance and bring the COM voltage back into regulation.

Considering these two effects, the R_LIM must provide enough current to compensate this offset current. The R_LIM must be low enough to provide enough current, but not too low otherwise the middle point voltage is corrected at each turn on and turn off edge of the gate driver and excessive power loss is generated.

The R_LIM resistor is chosen to provide enough current for the load using the following 3 equations, whichever has lowest value.

where

• Q_{G_Total} is the total gate charge of power switch.
• f_SW is the switching frequency of gate drive load.

• ∆I_{COM_SOURCE}=I_COM-VEE-I_VDD-COM, when I_COM-VEE>I_VDD-COM. Otherwise, ∆I_{COM_SOURCE}=0A.

where ∆I_{COM_SINK}=I_VDD-COM-I_COM-VEE, when I_COM-VEE<I_VDD-COM. Otherwise, ∆I_{COM_SINK}=0A.

Select R_LIM value to be the lowest of either 1) the R_LIM needed for capacitor imbalance and the load, calcualted by R_{LIM_MAX_H} and R_{LIM_MAX_L1}, or 2) the R_LIM needed to respond to a V_COM-VEE transient within 3 ms with the given load current, calcuated by R_{LIM_MAX_L2}.

R_LIM value determines response time of (COM – VEE) regulation. Too low an R_LIM value can cause oscillation and can overload (VDD – VEE). Too high an R_LIM value can give offset errors, due to slow response. If R_LIM is greater than above calculations, then there is not enough current available to replenish the charge to the output capacitors, causing a charge imbalance where the voltage is not able to maintain regulation, and eventually exceeds the OVP or UVP FAULT thresholds and shutting down the device for protection. Choose R_LIM value to be close but smaller than the smallest value of the three calculated results.

The power loss of R_LIM can be derived as

where Duty_RLIM is the duty cycle of RLIM-pin switch on-time respect to the switching cycle. 33% can be used as a reasonable rule of thumb for power loss calculation purpose.