JAJSPV4C February   2023  – March 2024 UCC14341-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Electrical Characteristics
    7. 6.7  Safety Limiting Values
    8. 6.8  Safety-Related Certifications
    9. 6.9  Insulation Characteristics
    10. 6.10 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 機能ブロック図
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Undervoltage Protection
        4. 7.3.4.4 Output Overvoltage Protection
        5. 7.3.4.5 Overpower Protection
        6. 7.3.4.6 Over-Temperature Protection
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 Single RLIM Resistor Selection
        3. 8.2.2.3 RDR Circuit Component Selection
        4. 8.2.2.4 Feedback Resistors Selection
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 関連資料
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

ENA and PG

The ENA input pin and PG output pin on the primary-side use 5V TTL and 3.3V LVTTL level logic thresholds.

The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter of the module. Either 3.3V or 5V logic rails can be used. Maintain the ENA pin voltage below 5.5V. After ENA pin voltage becomes above the enable threshold VEN_IR, UCC14341-Q1 enables, starts switching, goes through the soft-start process and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold VEN_IF, UCC14341-Q1 disables, stops switching.

The ENA pin can also be used to reset the UCC14341-Q1 device after it enters the protection safe-state mode. After a detected fault, the protection logic will latch off and place the device into a safe state. When all the faults are cleared, the ENA-pin can be used to clear the UCC14341-Q1 latch by toggling the ENA pin voltage below VEN_IF for longer than 150μs, then toggling back up to 3.3V or 5V. The device will then exit the latch-off mode and we initiate a soft-start. Figure 7-6 illustrates the latch-off reset timing.

GUID-4A4EB226-305D-49D4-AA56-DCAEBBD3D8AB-low.svg Figure 7-6 Latch-Off Reset Using ENA Pin

The active-low power-good (PG) pin is an open-drain output that indicates (short) when the module has no fault and the output voltages are within ±10% of the output voltage regulation setpoints. Connect a pull-up resistor (> 1kΩ) from PG pin to either a 5V or 3.3V logic rail. Maintain the PG pin voltage below 5.5V without exceeding its recommended operating voltage. The logic of PG pin can be illustrated using Figure 7-7.

GUID-2784548C-EA45-4ADD-A437-5B8FC5724361-low.svg Figure 7-7 PG Pin Logic