SLUSDU7
March 2020
UCC21320-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Functional Block Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety-Limiting Values
6.9
Electrical Characteristics
6.10
Switching Characteristics
6.11
Insulation Characteristics Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Propagation Delay and Pulse Width Distortion
7.2
Rising and Falling Time
7.3
Input and Disable Response Time
7.4
Programable Dead Time
7.5
Power-up UVLO Delay to OUTPUT
7.6
CMTI Testing
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VDD, VCCI, and Under Voltage Lock Out (UVLO)
8.3.2
Input and Output Logic Table
8.3.3
Input Stage
8.3.4
Output Stage
8.3.5
Diode Structure in the UCC21320-Q1
8.4
Device Functional Modes
8.4.1
Disable Pin
8.4.2
Programmable Dead Time (DT) Pin
8.4.2.1
Tying the DT Pin to VCC
8.4.2.2
DT Pin Connected to a Programming Resistor between DT and GND Pins
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Designing INA/INB Input Filter
9.2.2.2
Select External Bootstrap Diode and its Series Resistor
9.2.2.3
Gate Driver Output Resistor
9.2.2.4
Gate to Source Resistor Selection
9.2.2.5
Estimate Gate Driver Power Loss
9.2.2.6
Estimating Junction Temperature
9.2.2.7
Selecting VCCI, VDDA/B Capacitor
9.2.2.7.1
Selecting a VCCI Capacitor
9.2.2.7.2
Selecting a VDDA (Bootstrap) Capacitor
9.2.2.7.3
Select a VDDB Capacitor
9.2.2.8
Dead Time Setting Guidelines
9.2.2.9
Application Circuits with Output Stage Negative Bias
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DWK|14
MPCS001
サーマルパッド・メカニカル・データ
発注情報
slusdu7_oa
6.12
Typical Characteristics
VDDA = VDDB= 12 V, VCCI = 3.3 V, T
A
= 25°C, No load unless otherwise noted.
Figure 3.
Per Channel Current Consumption vs. Frequency (No Load, VDD = 12 V or 25 V)
Figure 5.
Per Channel Current Consumption (I
VDDA/B
) vs. Frequency (10-nF Load, VDD = 12 V or 25 V)
Figure 7.
Per Channel (I
VDDA/B
) Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching)
A.
Figure 9.
Rising and Falling Times vs. Load (VDD = 12 V)
Figure 11.
Propagation Delay vs. Temperature
A.
Figure 13.
Pulse Width Distortion vs. Temperature
Figure 15.
Propagation Delay Matching (t
DM
) vs. Temperature
Figure 17.
VDD 5-V UVLO Threshold vs. Temperature
Figure 19.
VDD
8-V
UVLO Threshold vs. Temperature
Figure 21.
IN/DIS Low Threshold
Figure 23.
Dead Time vs. Temperature (with R
DT
= 20 kΩ and 100 kΩ)
Figure 25.
Typical Output Waveforms
Figure 4.
Per Channel Current Consumption (I
VDDA/B
) vs. Frequency (1-nF Load, VDD = 12 V or 25 V)
Figure 6.
Per Channel (I
VDDA/B
) Supply Current Vs. Temperature (No Load, Different Switching Frequencies)
A.
Figure 8.
I
VCCI
Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching)
Figure 10.
Output Resistance vs. Temperature
Figure 12.
Propagation Delay vs. VCCI
Figure 14.
Propagation Delay Matching (t
DM
) vs. VDD
Figure 16.
VDD 5-V UVLO Hysteresis vs. Temperature
Figure 18.
VDD
8-V
UVLO Hysteresis vs. Temperature
Figure 20.
IN/DIS Hysteresis vs. Temperature
Figure 22.
IN/DIS High Threshold
Figure 24.
Dead Time Matching vs. Temperature (with R
DT
= 20 kΩ and 100 kΩ)