JAJSE13B October   2017  – July 2018 UCC21520-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Pulse Width Distortion
    2. 8.2 Rising and Falling Time
    3. 8.3 Input and Disable Response Time
    4. 8.4 Programable Dead Time
    5. 8.5 Power-up UVLO Delay to OUTPUT
    6. 8.6 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC21520-Q1
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 Tying the DT Pin to VCC
        2. 9.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 10.2.2.3 Gate Driver Output Resistor
        4. 10.2.2.4 Estimate Gate Driver Power Loss
        5. 10.2.2.5 Estimating Junction Temperature
        6. 10.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.6.1 Selecting a VCCI Capacitor
          2. 10.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.6.3 Select a VDDB Capacitor
        7. 10.2.2.7 Dead Time Setting Guidelines
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 認定
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins

If the DT pin is left open, the dead time duration (tDT) is set to <15 ns. One can program tDT by placing a resistor, RDT, between the DT pin and GND. The appropriate RDT value can be determined from from Equation 1, where RDT is in kΩ and tDT is in ns:

Equation 1. UCC21520-Q1 UCC21520A-Q1 Equation_01_SLUSCJ9.gif

The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when RDT=100kΩ. Therefore, It is recommended to parallel a ceramic capacitor, 2.2nF or above, close to the chip with RDT to achieve better noise immunity and better deadtime matching between two channels, especially when the dead time is larger than 300ns. The major consideration is that the current through the RDT is used to set the dead time, and this current decreases as RDT increases.

An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time. If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead time logic operating conditions are illustrated and explained in Figure 37:

UCC21520-Q1 UCC21520A-Q1 fig34_slusck0.gifFigure 37. Input and Output Logic Relationship With Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus, when INA goes high, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.