JAJSE13E October   2017  – June 2024 UCC21520-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Disable Response Time
    4. 6.4 Programable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21520-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead-Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Revision History

Changes from Revision D (June 2020) to Revision E (June 2024)

  • ドキュメント全体にわたって表、図、相互参照の採番方法を更新Go
  • 「特長」セクションから 5ns の最大遅延マッチングを削除Go
  • 伝搬遅延の標準値を 19ns から 33ns に変更Go
  • 10ns の最小パルス幅を 20ns に変更Go
  • 動作温度範囲を接合部温度範囲に変更Go
  • CMTI 仕様を 100V/ns から 125V/ns に変更Go
  • サージ耐性の値を 12.8kV から 10kV に変更Go
  • 「5ns 未満の入力パルスとノイズ過渡を除去」を削除Go
  • 「特長」の HBM および CDM ESD 分類レベルを削除Go
  • 安全認証を最新の規格に更新Go
  • 新しい仕様値に合わせて「概要」セクションを更新Go
  • Updated DT pin description to recommend ≤1nF capacitor on DT pinGo
  • Changed DT pin Min resistor recommendations from 500Ω to 2kΩGo
  • Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
  • Deleted ambient temperature specGo
  • Changed Max junction temp to 150CGo
  • Updated values from RθJA = 67.3°C/W, RθJC(top) = 34.4°C/W, RθJB = 32.1°C/W, ψJT = 18°C/W, ψJB = 31.6°C/W to RθJA = 69.8°C/W, RθJC(top) = 33.1°C/W, RθJB = 36.9°C/W, ψJT = 22.2°C/W, ψJB = 36°C/WGo
  • Updated values from PD = 1.05W, PDI = 0.05W, PDA/PDB = 0.5W to PD = 950mW, PDI = 50mW, PDA/PDB = 450mWGo
  • Updated values from DTI = >21mm, VIOSM = 8000VPK to DTI = >17mm, VIOSM = 10000VPK and added VIMP = 7692VPKGo
  • Deleted safety related certifications sectionGo
  • Updated values from IS = 75mA/36mA, PS = 50mW/900mW/900mW/1850mW to IS = 58mA/34mA, PS = 50mW/870mW/870mW/1790mW Go
  • Updated IVDDA/IVDDB quiescent current spec Max value from 1.8mA to 2.5mAGo
  • Updated IVCCI operating current Typ value from 2.0mA to 3.0mA and added Max value 3.5mAGo
  • Added IVDDA/IVDDB operating current Max = 4.2mAGo
  • Updated values from Rising threshold Min = 8.3V, Typ = 8.7V, Max = 9.2V to Min = 7.7V, Typ = 8.5V, Max = 8.9V Go
  • Updated values from Falling threshold Min = 7.8V, Typ = 8.2V, Max = 8.7V to Min = 7.2V, Typ = 7.9V, Max = 8.4V Go
  • Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
  • Updated Input high threshold Min value from 1.6V to 1.2VGo
  • Deadtime parameter broken to a its own table and added more parametersGo
  • Changed propagation delay TPDHL and TPDLH from Typ = 19ns, Max = 30ns to Typ = 33ns, Max = 45ns and adding Min = 26nsGo
  • Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
  • Added VCCI power up delay Go
  • Updated VDDA/VDDB power-up delay from Max = 100us to 10us Go
  • Updated CMTI from Min = 100V/ns to 125V/nsGo
  • Updated insulation curves to match updated characteristicsGo
  • Updated typical characteristics figuresGo
  • Updated Power-up UVLO Delay to OUTPUT section to match device electrical characteristics Go
  • Changed the Functional Block Diagram to add deglitch filter blockGo
  • Added paragraph on minimum pulse width to Output Stage sectionGo
  • Updated DT Pin Connected to a Programming Resistor Between DT and GND Pins section to recommend <1nF capacitor on DT pin. Go
  • Updated typical schematic DT pin capacitor recommendation Go
  • Updated Dead Time Setting Guidelines section to recommend <1nF capacitor on DT pin. Go

Changes from Revision C (March 2020) to Revision D (June 2020)

  • 「特長」の一覧に「機能安全品質管理」を追加Go

Changes from Revision B (July 2018) to Revision C (March 2020)

  • Changed DT pin description Go
  • Changed DT pin configuration recommendations Go
  • Added update to bootstrap circuit recommendations Go
  • Added update to gate resistor selection recommendations Go
  • Added gate to source resistor recommendation Go
  • Added update to Cboot selection recommendations Go

Changes from Revision A (May 2018) to Revision B (July 2018)

  • UCC21520A-Q1 事前情報のマーケティング ステータスを初期リリースに変更Go
  • Added detailed description for DISABLE Pin and DT PinGo
  • Added feature descriptions for UVLO delay to OUTPUT Go
  • Added bullet "It is recommended..." bullet to the component placement in the Layout Guidelines. Go

Changes from Revision * (October 2017) to Revision A (May 2018)

  • このデータシートに UCC21520A-Q1 デバイス (5V UVLO オプション) を追加Go
  • UCC21520A-Q1 事前情報を追加Go
  • Added typical curves of 5-V UVLO hysteresis and ON-OFF thresholdsGo