JAJSLH8A August   2020  – March 2021 UCC23511-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Function
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay, rise time and fall time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
  9. Device Functional Modes
    1. 9.1 ESD Structure
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Input Resistor
        2. 10.2.2.2 Gate Driver Output Resistor
        3. 10.2.2.3 Estimate Gate-Driver Power Loss
        4. 10.2.2.4 Estimating Junction Temperature
        5. 10.2.2.5 Selecting VCC Capacitor
      3. 10.2.3 Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Example

Figure 12-1 shows a PCB layout example with the signals and key components labeled.

GUID-00495931-5680-452F-9AF6-1E86F192DCC6-low.png
No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.
Figure 12-1 Layout Example

Figure 12-2 and Figure 12-3 show the top and bottom layer traces and copper.

GUID-C261AEBB-0DDB-4926-B6C4-89DD498BD9A4-low.gifFigure 12-2 Top-Layer Traces and Copper
GUID-1A5B5D5C-963E-4F1C-88E1-0C4F8B1DB452-low.gifFigure 12-3 Bottom-Layer Traces and Copper (Flipped)

Figure 12-4 shows the 3D layout of the top view of the PCB.

GUID-F35CDCD6-A341-464D-8D74-C54E87B0ED5D-low.png
The location of the PCB cutout between primary side and secondary sides ensures isolation performance.
Figure 12-4 3-D PCB View