JAJSKQ6B May   2020  – March 2021 UCC23513-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Function
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Rise Time and Fall Time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Resistor
        2. 9.2.2.2 Gate Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
        5. 9.2.2.5 Selecting VCC Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Insulation Specifications

PARAMETERTEST CONDITIONSSPECIFICATIONUNIT
CLRExternal clearance(1)Shortest terminal-to-terminal distance through air>8.5mm
CPGExternal Creepage(1)Shortest terminal-to-terminal distance across the package surface>8.5mm
DTIDistance through the insulationMinimum internal gap (internal clearance)>17µm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112>600V
Material GroupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE 0884-11 (VDE V 0884-11)(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)2121VPK
VIOWMMaximum isolation working voltageAC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 11500VRMS
DC voltage2121VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)		8000VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 62368, 1.2/50 ms waveform,
VTEST = 1.6 x VIOSM = 12800 VPK (qualification)		8000VPK
qpdApparent charge(4)Method a: After I/O safety test subgroup 2/3,Vini = VIOTM,
tini = 60 s; Vpd(m) = 1.2 x VIORM = 1800 VPK, tm = 10 s		≤5pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 x VIORM = 2400 VPK, tm = 10 s≤5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875  x  VIORM = 2813 VPK, tm = 1 s		≤5
CIOBarrier capacitance, input to output(5)VIO = 0.4 x sin (2πft), f = 1 MHz0.5pF
RIOInsulation resistance, input to output(5)VIO = 500 V, TA = 25°C>1012Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C>1011
VIO = 500 V at TS = 150°C>109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 x VISO = 6840 VRMS, t = 1 s (100% production)		5700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.