DATA SHEET
UCC24610 GREEN Rectifier™ Controller Device
1 Features
- Secondary-Side Controller Optimized for 5-V Systems
- Up to 600-kHz Operating Frequency
- VDS MOSFET-Sensing
- 1.6-Ω Sink, 2.0-Ω Source Gate-Drive Impedances
- Micro-Power Sleep Current for 90+ Designs
- Automatic Light-Load Management
- Synchronous Wake-Up From Sleep and Light-Load Modes
- Protection Features on Programming Inputs
- SYNC Input for CCM Operation
- 20-ns Typical Turnoff Propagation Delay
- Improved Efficiency and Design Flexibility Over Traditional Diode Solution
- May Be Biased Directly From 5-V Output
- Minimal Component Count
2 Applications
- AC-to-DC 5-V Adapters
- 5-V Bias Supplies
- Low Voltage Rectification Circuits
- Flyback and LLC Converters
3 Description
This GREEN Rectifier™ controller is a high-performance controller and driver for standard and logic-level N-channel MOSFET power devices used for low-voltage secondary-side synchronous rectification.
The combination of controller and MOSFET emulates a near-ideal diode rectifier. This solution not only directly reduces power dissipation of the rectifier but also indirectly reduces primary-side losses as well, due to compounding of efficiency gains.
Using drain-to-source voltage sensing, the UCC24610 is ideal for Flyback and LLC-resonant power supplies but can also be used with other power architectures. The UCC24610 is optimized for output voltages from 4.5 V to 5.5 V, and is suitable for use with lower and higher output voltages as well.
The UCC24610 offers a programmable false-triggering filter, a programmable timer to automatically switch to light-load mode at light load, and a SYNC input for optional use in continuous conduction mode (CCM) systems. Protection features on TON and EN/TOFF pins prevent run-away on-time due to open-circuit or short-circuit fault conditions.
This device is available in an 8-pin SOIC package and an 8-pin, 3.0-mm × 3.0-mm SON package with an exposed thermal pad.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| UCC24610DRB | SON (8) | 3.00 mm × 3.00 mm |
| UCC24610D | SOIC (8) | 4.90 mm × 3.91 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Flyback Topology
LLC-Resonant Half Bridge
4 Revision History
Changes from B Revision (September 2010) to C Revision
- Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
DRB Package
8-Pin SON With Exposed Thermal Pad
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| EN/TOFF | 2 | I |
EN/TOFF (combined enable function and programmable off-time timer), when VCC falls below the VCC(off) threshold, the UCC24610 is in UVLO mode, the EN/TOFF input is internally connected to GND through a 10-kΩ resistance and the internal current source is turned off. When VCC exceeds the VCC(on) threshold, the 10-kΩ resistance is removed and the current source is turned on. Thereafter, when EN/TOFF exceeds VEN(on), the UCC24610 is in run mode and when EN/TOFF falls below VEN(off), the UCC24610 is in sleep mode. The voltage level on EN/TOFF also programs the minimum off-time (TOFF) for the controlled MOSFET. EN/TOFF is internally driven by a two-level current source, so the voltage level on EN/TOFF can be set by connecting a resistor from EN/TOFF to GND. The EN/TOFF current source initially drives twice as much current (IEN-START) to achieve the enable threshold voltage VEN(on), and then drops to the normal run mode level (IEN-ON) to program the TOFF time. Alternatively, the desired EN/TOFF voltage may be forced using an external source. The TOFF time is programmed to suppress GATE output for a desired duration to avoid possible false retriggering from resonant ringing or noise after turnoff. The TOFF timer is triggered when VD voltage exceeds 1.5 V after GATE transitions from high to low. |
| GATE | 5 | O |
GATE (controlled MOSFET gate drive), connect GATE to the gate of the controlled MOSFET through a small series resistor using short PC board tracks to achieve optimal switching performance. The GATE output can achieve >1-A peak source current when High and >2-A peak sink current when Low into a large N-channel power MOSFET. In sleep mode and UVLO, GATE impedance to GND is about 1.6 Ω. GATE impedance to GND crests about 80 Ω, when VCC ≈ 1.1 V. |
| GND | 6 | – |
GND (combined analog and power ground), this ground input is the reference potential for the GATE driver, the UVLO comparator, the EN/TOFF comparator, the EN/TOFF timer, and the TON timer. Connect a 0.1-µF or larger ceramic bypass capacitor from the VCC pin to the GND pin through very short PC-board tracks. |
| SYNC | 1 | I |
SYNC (gate turnoff synchronization), a falling edge on SYNC immediately forces GATE low, turning off the controlled MOSFET asynchronous to the voltage on the drain and source, and regardless of the state of the TON timer. When a power converter is operated in continuous conduction mode (CCM), it is necessary to turn off the controlled MOSFET under command of the switching converter. Connect SYNC to a control signal on the primary side of the converter using a high-voltage isolation capacitor or transformer, or other suitable coupling means. A continuous low level on the SYNC input causes GATE to be driven low for the same duration. |
| TON | 3 | I |
TON (programmable on-time timer), program the minimum on time with a resistor from TON to GND. When the controlled MOSFET gate is turned on, some ringing noise is generated. The minimum on-time timer blanks the VD-VS comparator, keeping the controlled MOSFET on for at least the programmed minimum time. This time also determines the light-load shut-down point. If VD-VS falls below the –5-mV threshold before TON time expires, the controller transitions into light-load mode on the next switching cycle. When VD-VS falls below the –5-mV threshold after TON expires, the device resumes run-mode operation on the next switching cycle. |
| VCC | 4 | I |
VCC (positive power input), connect a DC power voltage to VCC. Bypass VCC to GND with a 0.1-µF or larger ceramic capacitor using short PC board tracks. VCC supplies power to all circuits in the UCC24610. Under-Voltage Lockout (UVLO) comparators prevent operation until VCC rises above VCC(on). VCC can be used to safely turn off the UCC24610 by pulling VCC below VCC(off). In the event that VCC drops below VCC(off), GATE immediately falls Low and EN/TOFF is internally connected to GND with a 10-kΩ resistance. |
| VD | 8 | I |
VD (drain-sense voltage), connect this pin as close as possible to the controlled MOSFET drain pad through a short PC board track, to minimize the effects of trace inductance on VD. VD must be >1.5 V and the TOFF timer must be expired before the device may be armed to allow the controlled MOSFET to be turned on the next switching cycle. Once armed, the controlled MOSFET is turned on (GATE goes High) when VD falls more than –150 mV below VS. At that threshold, the GATE output goes High and the TON timer is triggered. GATE remains High at least as long as the programmed TON time has not expired, unless a pulse at the SYNC input is detected. After TON has expired, the GATE output is turned off when VD-VS voltage decreases to –5 mV. If VD-VS decreases to –5 mV before TON expires, the controller enters light-load mode and the GATE pulse for the next switching cycle is suppressed. When the VD voltage increases to 1.5 V, the TOFF timer is triggered and the GATE output is prevented from turning on during the TOFF interval. |
| VS | 7 | I |
VS (source-sense voltage), connect this pin as close as possible to the controlled MOSFET source pad through a short PC-board track, to minimize the effects of trace inductance on VS. |
| Thermal Pad | – |
Thermal Pad on SON package only, the exposed thermal pad on the bottom of the SON package enhances the thermal performance of the device, and is intended to be soldered to a heat-dissipating pad on the PCB. This pad should be connected to the GND pin, or may be left floating (unconnected to any network). It is internally connected to GND through an indeterminate impedance and so may not be used to carry current. |
|
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Input voltage (6) | VCC | –0.3 | 6.5 | V |
| EN/TOFF(2) | –0.3 | VCC | V | |
| TON(3) | –0.3 | VCC | V | |
| VD for IVD ≤ –10 mA | –1.0 | 50 | V | |
| VS for IVS ≤ –10 mA | –1.0 | 0.5 | V | |
| Input current, peak | SYNC(4) pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1% | ±100 | mA | |
| Output current, peak | GATE(5) pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1% | ±3 | A | |
| TJ | Operating junction temperature | –40 | 125 | °C |
| Tstg | Storage temperature | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) EN/TOFF can be driven by a voltage within the specified absolute maximum range or connected to a resistor to ground. Either method will program maximum off-time. When programmed by a resistor to GND, the voltage at the EN/TOFF terminal is internally limited to <VCC regardless of resistor value, so no absolute maximum input voltage considerations are required.
(3) In normal use, TON is connected to a resistor to GND. TON is normally not connected to a voltage source. When TON is connected to ground through a resistor, no absolute maximum input voltage considerations are required.
(4) In normal use, SYNC is connected with a capacitor to a high-speed voltage-transition source. The capacitor value shall be selected in conjunction with the worst-case voltage slew-rate to insure that the current into or out of SYNC is not in excess of the SYNC absolute maximum input current rating, or a current-limiting series resistor may also be necessary. In this use, if the input current is limited to less than the absolute maximum, no absolute maximum input voltage considerations are required. The capacitor breakdown voltage shall be selected to insure that dangerous voltage is not applied to the UCC24610. Continuous SYNC current is subject to the maximum operating junction temperature limitation.
(5) In normal use, GATE is connected to the gate of a power MOSFET through a small resistor. When used this way, GATE current is limited by the UCC24610 and no absolute maximum output current considerations are required. The series resistor shall be selected to minimize overshoot and ringing due to series inductance of the GATE output and power-MOSFET gate-drive loop. Continuous GATE current is subject to the maximum operating junction temperature limitation.
(6) Input voltages more negative than indicated may exist on any listed pin without excess stress or damage to the device if the pin’s input current magnitude is limited to less than -10mA. See separate ratings for SYNC and GATE pins.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2,000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | V | ||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VIN | VCC input voltage | 4.5 | 5.5 | V | |
| CVCC | VCC bypass capacitor | 0.1 | µF | ||
| TJ | Junction temperature | –40 | 125 | °C | |
| fS | Switching frequency | 20 | 600 | kHz | |
| RTON | TON-to-GND resistor | 10 | 261 | kΩ | |
| REN/TOFF | EN/TOFF-to-GND resistor | 93 | 280 | kΩ | |
| tMIN | SYNC minimum pulse width at VTHSYNC – 0.1 V | 20 | ns | ||
6.4 Thermal Information
| THERMAL METRIC(1) | UCC24610 | UNIT | ||
|---|---|---|---|---|
| DRB (SON) | D (SOIC) | |||
| 9 PINS | 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 48.3 | 115.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 53.7 | 59.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 23.5 | 54.3 | °C/W |
| ψJT | Junction-to-top characterization parameter | 1.2 | 13.1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 23.7 | 53.8 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 8.1 | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
At VCC = 5 VDC, CGATE = 0 pF, RTON = 200 kΩ, REN/TOFF = 100 kΩ, −40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to GND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BIAS SUPPLY | ||||||
| ICCSTART | VCC current, undervoltage | VCC = 4.05 V | 70 | 100 | μA | |
| ICCSTBY | VCC current, disabled | VCC = 5.5 V, REN/TOFF = 0 Ω | 130 | 200 | μA | |
| ICCON | VCC current, enabled | VCC = 5.5 V, REN/TOFF = 100 kΩ | 1.40 | 2.15 | 2.80 | mA |
| VENON | EN/TOFF turnon threshold, rising | EN/TOFF driven, ICC > 1 mA | 1.31 | 1.40 | 1.49 | V |
| VENOFF | EN/TOFF turnoff threshold, falling | EN/TOFF driven, ICC < 200 µA | 0.74 | 0.80 | 0.86 | V |
| IEN-START | EN/TOFF input current, disabled | EN/TOFF = 1.3 V, rising from zero | –21.5 | –20.0 | –18.5 | μA |
| IEN-ON | EN/TOFF input current, enabled | EN/TOFF = 2 V | –10.7 | –10.0 | –9.3 | μA |
| UNDERVOLTAGE LOCKOUT (UVLO) | ||||||
| VCCON | VCC turnon threshold | Turnon detected by VEN > 1.0 V | 4.15 | 4.40 | 4.65 | V |
| VCCOFF | VCC turnoff threshold | Turnoff detected by VEN < 0.5 V | 3.96 | 4.20 | 4.44 | V |
| VCCHYST | UVLO hysteresis | VCCHYST = VCCON – VCCOFF | 0.15 | 0.20 | 0.25 | V |
| MOSFET VOLTAGE SENSING | ||||||
| VTHARM | GATE rearming threshold | VD to GND, rising | 1.3 | 1.5 | 1.7 | V |
| VTHON | GATE turnon threshold | (VD – VS) falling, VS = 0 V | –220 | –150 | –80 | mV |
| VTHOFF | GATE turnoff threshold | (VD – VS) rising, VS = 0 V | –8 | –5 | –2 | mV |
| IDH | VD input bias current, high | VD = 50 V, VS = 0 V | 0.05 | 2.00 | μA | |
| IDL | VD input bias current, low | VD = -0.15 V, VS = 0 V | –250 | –150 | –50 | μA |
| IS | VS input bias current | VD = 0 V, VS = 0 V | –250 | –150 | –50 | μA |
| GATE DRIVER | ||||||
| rGUP | GATE pullup resistance, enabled | IGATE = –100 mA | 2.0 | 3.6 | Ω | |
| rGDN | GATE pulldown resistance, enabled | IGATE = 100 mA | 1.6 | 2.5 | Ω | |
| VOHG | GATE output high voltage | IGATE = –100 mA | 4.64 | 4.80 | V | |
| VOLG | GATE output low voltage | IGATE = 100 mA | 0.16 | 0.25 | V | |
| VOLGUV | GATE output low voltage, UV | IGATE = 25 mA, VCC = 0 V | 0.70 | 0.90 | V | |
| VOLGOFF | GATE output low voltage, disabled | IGATE = 25 mA, VEN = 0 V | 0.04 | 0.10 | V | |
| SYNCHRONIZATION | ||||||
| VTHSYNC | SYNC falling threshold | GATE output transitions from high to low | VCC – 2.4 | VCC – 2.0 | VCC – 1.6 | V |
| rSYNC | SYNC pullup resistance | Internal resistance from SYNC to VCC | 1.6 | 2.0 | 2.4 | kΩ |
6.6 Timing Requirements
At VCC = 5 VDC, CGATE = 0 pF, RTON = 200 kΩ, REN/TOFF = 100 kΩ, −40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to GND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C.| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| MOSFET VOLTAGE SENSING | |||||
| tDON | GATE turnon propagation delay, from VTHON to GATE > 1 V | 44 | 70 | ns | |
| tDOFF | GATE turnoff propagation delay, from VTHOFF to GATE < 4 V | 16 | 35 | ns | |
| MINIMUM ON-TIME SETTING | |||||
| tONLR | Minimum on-time, low resistance, RTON = 16.5 kΩ | 0.17 | 0.25 | 0.33 | μs |
| tONHR | Minimum on-time, high resistance, RTON = 200 kΩ | 2.2 | 3.0 | 3.8 | μs |
| MINIMUM OFF-TIME SETTING | |||||
| tOFFLR | Minimum off-time, low resistance, REN/TOFF = 100 kΩ | 4.94 | 7.80 | 9.86 | μs |
| tOFFHR | Minimum off-time, high resistance, REN/TOFF = 261 kΩ | 0.55 | 1.37 | 2.30 | μs |
| tOFFLV | Minimum off-time, low voltage, EN/TOFF = 1.0 V | 4.94 | 7.80 | 9.86 | μs |
| tOFFHV | Minimum off-time, high voltage, EN/TOFF = 2.61 V | 0.85 | 1.37 | 2.10 | μs |
| tOFFOV | Minimum off-time, over voltage, 3 V < VEN < VCC | 0.48 | 0.65 | 0.82 | μs |
| GATE DRIVER | |||||
| tfGATE | GATE rise time, from 1 V to 4 V, CGATE = 3300 pF | 14 | 30 | ns | |
| trGATE | GATE fall time, from 4 V to 1 V, CGATE = 3300 pF | 9 | 25 | ns | |
| tDIS | Disable delay, from EN falling to GATE falling | 50 | 100 | 150 | ns |
| SYNCHRONIZATION | |||||
| tSDLY | SYNC propagation delay, from SYNC falling to GATE falling 10% | 20 | 60 | ns | |
6.7 Typical Characteristics
