JAJSEQ5A August   2017  – February 2018 UCC24612

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハイサイドSRによるフライバック
      2.      ローサイドSRによるフライバック
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Management
      2. 7.3.2 Synchronous Rectifier Control
      3. 7.3.3 Adaptive Blanking Time
        1. 7.3.3.1 Turn-On Blanking Timer (Minimum On Time)
        2. 7.3.3.2 Turn-Off Blanking Timer
        3. 7.3.3.3 SR Turn-on Re-arm
      4. 7.3.4 Gate Voltage Clamping
      5. 7.3.5 Standby Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 UVLO Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Run Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SR MOSFET Selection
        2. 8.2.2.2 Bypass Capacitor Selection
        3. 8.2.2.3 Snubber design
        4. 8.2.2.4 High-Side Operation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Steady State Testing Low-Side Configuration
        2. 8.2.3.2 Steady State Testing High-Side Configuration
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 コミュニティ・リソース
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Power Management

The UCC24612 SR controller is powered from REG pin through the internal linear regulator between VDD pin and REG pin. This configuration allows optimal design of the gate driver stage to achieve fast driving speed, low driving loss and higher noise immunity.

In low-side SR configuration, as shown in Figure 13, the UCC24612 is powered from the output voltage directly.

UCC24612 LSFlyback.gifFigure 13. UCC24612 Used in Low-side SR Configuration

During start up, the output voltage rises from zero. With the rising of output voltage, the internal linear regulator operates in a pass-through mode, and the REG pin voltage rises together with the output voltage. The UVLO function of UCC24612 monitors the voltage on the REG pin instead of the VDD pin. Before REG pin voltage rises above UVLO on threshold VREGON, UCC24612 consumes the minimum current IVDDSTART. Once the REG voltage rises above VREGON, the device starts to consume the full operating current and controls the switching of the SR MOSFET.

When VDD voltage is above 9.5 V, the internal linear regulator operates in regulator mode. The REG pin is well regulated at 9.5 V. This voltage level is chosen to give a good compromise between SR conduction loss and gate drive loss. The internal regulator is rated at 10 mA of average load regulation capability for higher switching frequency operation. It is required to have a sufficient bypass capacitor on the REG pin to ensure stable operation of the linear regulator. A 2.2-µF bypass capacitor is recommended.

When VDD voltage is below 9.5 V, the internal linear regulator operates in pass-through mode. Depending on the load current, the regulator has a voltage drop of approximately 0.2 V. The UCC24612 continues to operate during this mode until the REG pin voltage drops below UVLO turn off level VREGOFF.

A typical timing diagram of VDD and REG pin voltage can be found in Figure 14.

UCC24612 PLRLowside.gifFigure 14. Timing Diagram for VDD and REG in Low-side SR Configuration

In some applications, such as USB chargers, the converter is required to deliver the full output current when the output is over loaded and output voltage drops below the regulation level. In 5-V applications, the output voltage could drop too low to adequately turn on the SR. In this case, the UCC24612 can be powered through a simple external R-C-D circuit, as shown in Figure 15. Due to the wide voltage range handling capability, this simple circuit provides power from the SR drain voltage. Even though this method easily powers up the device, this is a very inefficient way of powering the controller. A more efficient way would be to use an auxiliary winding to provide the power.

UCC24612 LSDCR.gifFigure 15. UCC24612 Used in Low-side and Low Output Voltage Condition

The same biasing method can also maintain the SR controller operation in high-side SR configuration, as shown in Figure 16. More details about biasing UCC24612 can be found in Power Supply Recommendations.

UCC24612 HSFlyback.gifFigure 16. UCC24612 Used in High-Side SR Configuration