JAJSEQ5A August   2017  – February 2018 UCC24612

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハイサイドSRによるフライバック
      2.      ローサイドSRによるフライバック
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Management
      2. 7.3.2 Synchronous Rectifier Control
      3. 7.3.3 Adaptive Blanking Time
        1. 7.3.3.1 Turn-On Blanking Timer (Minimum On Time)
        2. 7.3.3.2 Turn-Off Blanking Timer
        3. 7.3.3.3 SR Turn-on Re-arm
      4. 7.3.4 Gate Voltage Clamping
      5. 7.3.5 Standby Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 UVLO Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Run Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SR MOSFET Selection
        2. 8.2.2.2 Bypass Capacitor Selection
        3. 8.2.2.3 Snubber design
        4. 8.2.2.4 High-Side Operation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Steady State Testing Low-Side Configuration
        2. 8.2.3.2 Steady State Testing High-Side Configuration
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 コミュニティ・リソース
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 Gate Voltage Clamping

With the wide VDD voltage range capability, UCC24612 clamps the gate driver voltage to a maximum level of 9.5 V to allow fast driving speed, low driving loss and compatibility with different MOSFETs. The 9.5-V level is chosen to minimize the conduction loss for the non-logic level MOSFETs.

The gate driver voltage clamp is achieved through the regulated REG pin voltage. When VDD voltage is above 9.5 V, the linear regulator regulates the REG pin voltage to be 9.5 V, which is also the power supply of the gate driver stage. This way, the MOSFET gate is clamped at 9.5 V, regardless of how high the VDD voltage is. When the VDD voltage is close to or below the programmed REG pin regulation voltage, UCC24612 can no longer regulate the REG pin voltage. Instead, it enters a pass-through mode where the REG pin voltage follows the VDD pin voltage with slight voltage drop out (VREGDO). During this time, the gate driver voltage is lower than its programmed value but still provides SR driving capability. The UCC24612 is disabled once the REG pin voltage drops below its UVLO level.