JAJSEQ5A August   2017  – February 2018 UCC24612

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハイサイドSRによるフライバック
      2.      ローサイドSRによるフライバック
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Management
      2. 7.3.2 Synchronous Rectifier Control
      3. 7.3.3 Adaptive Blanking Time
        1. 7.3.3.1 Turn-On Blanking Timer (Minimum On Time)
        2. 7.3.3.2 Turn-Off Blanking Timer
        3. 7.3.3.3 SR Turn-on Re-arm
      4. 7.3.4 Gate Voltage Clamping
      5. 7.3.5 Standby Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 UVLO Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Run Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SR MOSFET Selection
        2. 8.2.2.2 Bypass Capacitor Selection
        3. 8.2.2.3 Snubber design
        4. 8.2.2.4 High-Side Operation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Steady State Testing Low-Side Configuration
        2. 8.2.3.2 Steady State Testing High-Side Configuration
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 コミュニティ・リソース
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.4 High-Side Operation

To use the UCC24612EVM to replace a high-side rectifier requires removing jumper JP1 and connecting the EVM as shown in Figure 23. Please note that the EVM comes with a default VDD filtering resistor (R2) of 20 kΩ. However, resistor R2 needs to be adjusted based on your individual application.

UCC24612 Figure-5.gifFigure 23. UCC24612-1EVM Used in High-Side Rectifier Application

If the magnitude of the voltage from TP2 to TP1 is less than 28 V, remove R2 that is populated on the EVM ( 20 kΩ) and set R2 to 0 to 10 ohms and remove 27-V Zener diode D1 from the board.

If TP2 to TP1 is greater than 28 V use resistor R2 to setup an averaging filter to lower the DC voltage applied to VDD.

The RC filter formed by C2 and R2 should set the filter pole frequency to one-hundredth of the converter's maximum switching frequency. In this example the converter's maximum switching frequency (fSW) is 85 kHz. Note that the switching frequency will vary based on design and preference.

Equation 6. UCC24612 Eq4.gif

When the RC filter circuit is used, it is recommended that the VDD voltage should be between 4 V to 28 V to provide enough energy and voltage to the gate driver. This range can be determined in a fixed frequency Flyback converter with the following equations. DMAX is the maximum duty cycle of the converter and DMIN is the minimum duty cycle of the converter. NP is the Flyback transformer (T1) primary number of turns and NS is the transformer secondary number of turns. Please refer to Figure 23 for details.

Maximum VDD voltage (VVDD(MAX)):

Equation 7. UCC24612 Equation-5.gif

Minimum VDD voltage (VVDD(MIN)):

Equation 8. UCC24612 Equation-6.gif