JAJSEQ5A August   2017  – February 2018 UCC24612

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハイサイドSRによるフライバック
      2.      ローサイドSRによるフライバック
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Management
      2. 7.3.2 Synchronous Rectifier Control
      3. 7.3.3 Adaptive Blanking Time
        1. 7.3.3.1 Turn-On Blanking Timer (Minimum On Time)
        2. 7.3.3.2 Turn-Off Blanking Timer
        3. 7.3.3.3 SR Turn-on Re-arm
      4. 7.3.4 Gate Voltage Clamping
      5. 7.3.5 Standby Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 UVLO Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Run Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SR MOSFET Selection
        2. 8.2.2.2 Bypass Capacitor Selection
        3. 8.2.2.3 Snubber design
        4. 8.2.2.4 High-Side Operation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Steady State Testing Low-Side Configuration
        2. 8.2.3.2 Steady State Testing High-Side Configuration
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 コミュニティ・リソース
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

5-Pin SOT-23
UCC24612 Pinout.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
REG 3 O
REG is the device bias pin. An internal linear regulator from VDD to REG generates a well regulated 9.5-V voltage. It is recommend to put a 2.2-µF bypass capacitor from REG pin to VS pin.
VD 5 I
MOSFET drain voltage sensing input. Connect this pin to SR MOSFET drain pin. The layout should avoid sharing the VD pin trace with the power path to minimize the impact of parasitic inductance.
VDD 4 I
Internal linear regulator input. Connect this pin to the output voltage when in low-side SR configuration. Use R-C-D circuit or other circuits to generate bias voltage from SR MOSFET drain when using high-side SR configuration, referring to Power Supply Recommendations for details.
VG 1 O
VG (controlled MOSFET gate drive), connect VG to the gate of the controlled MOSFET through a small series resistor using short PC board tracks to achieve optimal switching performance. The VG output can achieve >1-A peak source current when High and >4-A peak sink current when Low when connected to a large N-channel power MOSFET. Due to the weak internal pull up after initial fast turn on, avoid putting a resistor less than 50 kΩ between VG to VS .
VS 2 -
VS is the internal ground reference of the UCC24612. It is also used to sense the voltage drop across the SR MOSFET. The layout should avoid sharing the VS pin trace with the power path to minimize the impact of parasitic inductance.