SLUSCG0B December 2015 – July 2024 UCC27211A-Q1
PRODUCTION DATA
Generally, the switching speed of the power switch during turnon and turnoff should be as fast as possible in order to minimize switching power losses. The gate driver device must be able to provide the required peak current for achieving the targeted switching speeds with the targeted power MOSFET. The system requirement for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dVDS/dt). For example, the system requirement might state that a SPP20N60C3 power MOSFET must be turned-on with a dVDS/dt of 20V/ns or higher with a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC-converter application. This type of application is an inductive hard-switching application and reducing switching power losses is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET turnon event (from 400V in the OFF state to VDS(on) in on state) must be completed in approximately 20ns or less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (QGD parameter in the SPP20N60C3 data sheet is 33nC typical) is supplied by the peak current of gate driver. According to power MOSFET inductive switching mechanism, the gate-to-source voltage of the power MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage of the power MOSFET, VGS(TH).
To achieve the targeted dVDS/dt, the
gate driver must be capable of providing the QGD charge in 20ns or less.
In other words a peak current of 1.65A (= 33nC / 20ns) or higher must be provided by
the gate driver. The UCC27211A gate driver is capable of providing 4A peak sourcing
current which clearly exceeds the design requirement and has the capability to meet
the switching speed needed. The 2.4× overdrive capability provides an extra margin
against part-to-part variations in the QGD parameter of the power MOSFET
along with additional flexibility to insert external gate resistors and fine tune
the switching speed for efficiency versus EMI optimizations. However, in practical
designs the parasitic trace inductance in the gate drive circuit of the PCB will
have a definitive role to play on the power MOSFET switching speed. The effect of
this trace inductance is to limit the dI/dt of the output current pulse of the gate
driver. In order to illustrate this, consider output current pulse waveform from the
gate driver to be approximated to a triangular profile, where the area under the
triangle
(½ × IPEAK × time) would equal
the total gate charge of the power MOSFET (QG parameter in SPP20N60C3 power MOSFET
datasheet = 87nC typical). If the parasitic trace inductance limits the dI/dt then a
situation may occur in which the full peak current capability of the gate driver is
not fully achieved in the time required to deliver the QG required for the power
MOSFET switching. In other words the time parameter in the equation would dominate
and the IPEAK value of the current pulse would be much less than the true
peak current capability of the device, while the required QG is still delivered.
Because of this, the desired switching speed may not be realized, even when
theoretical calculations indicate the gate driver is capable of achieving the
targeted switching speed. Thus, placing the gate driver device very close to the
power MOSFET and designing a tight gate drive-loop with minimal PCB trace inductance
is important to realize the full peak-current capability of the gate driver.