JAJSIT3B March   2020  – April 2022 UCC27284

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History B
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-Up and UVLO
      3. 7.3.3 Input Stage
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.4 Delays and Pulse Width

The total delay encountered in the PWM, driver and power stage need to be considered for a number of reasons, primarily delay in current limit response. Also to be considered are differences in delays between the drivers which can lead to various concerns depending on the topology. The synchronous buck topology switching requires careful selection of dead-time between the high-side and low-side switches to avoid cross conduction as well as excessive body diode conduction.

Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the high-side and low-side pulse widths in any operating condition. The UCC27284 device has maximum propagation delay, across process, and temperature variation, of 30 ns and delay matching of 7 ns, which is one of the best in the industry.

Narrow input pulse width performance is an important consideration in gate driver devices, because output may not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively wide steady state PWM output signals from controller, very narrow pulses may be encountered under following operating conditions.

  • soft-start period
  • large load transients
  • short circuit conditions

These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to respond properly to these narrow signals.

Figure 8-2 shows that the UCC27284 device produces reliable output pulse even when the input pulses are very narrow and bias voltages are very low. The propagation delay and delay matching do not get affected when the input pulse width is very narrow.

GUID-3D6C074E-D905-46C5-A0A8-ACE91168BFD5-low.gifFigure 8-2 Input and Output Pulse Width